Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 88

B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
8
7
6:6
5
4
3
2:0
88
0/1/0–2/PCI
6–7h
0010h
RW1C, RO, RO-V
16 bits
0h
Reset RST/
Attr
Value PWR
RW1C 0b Uncore
RO 0b Uncore
RO 0h
RO 0b Uncore
RO 1b Uncore
RO-V 0b Uncore
RO 0h
Processor Configuration Registers
Description
Master Data Parity Error (PMDPE)
This bit is Set by a Requester (Primary Side for Type 1
Configuration Space header Function) if the Parity Error Response
bit in the Command register is 1b and either of the following two
conditions occurs:
• Requester receives a Completion marked poisoned
• Requester poisons a write Request
If the Parity Error Response bit is 0b, this bit is never Set.
This bit will be set only for completions of requests encountering
ECC error in DRAM.
Poisoned Peer-to-peer posted forwarded will not set this bit. They
are reported at the receiving port.
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
Capabilities List (CAPL)
Indicates that a capabilities list is present. Hardwired to 1.
INTx Status (INTAS)
Indicates that an interrupt message is pending internally to the
device. Only PME and Hot Plug so urces feed into this status bit (not
PCI INTA-INTD assert and deassert messages). The INTA Assertion
Disable bit, PCICMD1[10], has no effect on this bit.
Note that INTA emulation interrupts received across the link are
not reflected in this bit.
Reserved
Datasheet, Volume 2