Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 7

2.12.13
2.12.14
2.12.15
2.12.16
2.12.17
2.12.18
2.12.19
2.12.20
2.12.21
2.12.22
2.12.23
2.13 MCHBAR Registers in Memory Controller - Channel 0 ........................................... 204
2.13.1
2.13.2
2.13.3
2.14 MCHBAR Registers in Memory Controller - Channel 1 ........................................... 206
2.14.1
2.14.2
2.14.3
2.15 MCHBAR Registers in Memory Controller -
Integrated Memory Peripheral Hub (IMPH).......................................................... 208
2.15.1
2.16 MCHBAR Registers in Memory Controller - Common............................................. 209
2.16.1
2.16.2
2.16.3
2.16.4
2.17 Memory Controller MMIO Registers Broadcast Group ............................................ 213
2.17.1
2.17.2
2.17.3
2.18 Integrated Graphics VTd Remapping Engine Registers .......................................... 215
2.18.1
2.18.2
2.18.3
2.18.4
2.18.5
2.18.6
2.18.7
2.18.8
2.18.9
2.18.10
2.18.11
2.18.12
2.18.13
2.18.14
2.18.15
2.18.16
2.18.17
2.18.18
2.18.19
2.18.20
2.18.21
2.18.22
2.18.23
2.18.24
Datasheet, Volume 2
DMIVCPRSTS-DMI VCp Resource Status Register ................................. 194
DMIESD-DMI Element Self Description Register ................................... 195
DMILE1D-DMI Link Entry 1 Description Register................................... 196
DMILE1A-DMI Link Entry 1 Address Register........................................ 196
DMILE2D-DMI Link Entry 2 Description Register................................... 197
DMILE2A-DMI Link Entry 2 Address Register........................................ 197
LCAP-Link Capabilities Register .......................................................... 198
LCTL-Link Control Register ................................................................ 199
LSTS-DMI Link Status Register .......................................................... 200
LCTL2-Link Control 2 Register ........................................................... 201
LSTS2-Link Status 2 Register ............................................................ 203
PM_PDWN_config_C0-Power-down Configuration Register ..................... 204
TC_RFP_C0-Refresh Parameters Register ............................................ 205
TC_RFTP_C0-Refresh Parameters Register .......................................... 205
PM_PDWN_Config_C1-Power-down Configuration Register..................... 206
TC_RFP_C1-Refresh Parameters Register ............................................ 207
TC_RFTP_C1-Refresh Timing Parameters Register ................................ 207
CRDTCTL3-Credit Control 3 Register................................................... 208
MAD_CHNL-Address Decoder Channel Configuration Register................. 209
MAD_DIMM_ch0-Address decode channel 0 Register ............................ 210
MAD_DIMM_ch1 - Address Decode Channel 1 Register ........................... 211
PM_SREF_config-Self Refresh Configuration Register ............................ 212
PM_PDWN_Config-Power-down Configuration Register .......................... 213
PM_CMD_PWR-Power Management Command Power Register................ 214
PM_BW_LIMIT_config-BW Limit Configuration Register ......................... 214
VER_REG-Version Register ................................................................ 216
CAP_REG-Capability Register............................................................. 217
ECAP_REG-Extended Capability Register ............................................. 220
GCMD_REG-Global Command Register................................................ 222
GSTS_REG-Global Status Register...................................................... 225
RTADDR_REG-Root-Entry Table Address Register................................. 226
CCMD_REG-Context Command Register.............................................. 227
FSTS_REG-Fault Status Register ........................................................ 229
FECTL_REG-Fault Event Control Register............................................. 231
FEDATA_REG-Fault Event Data Register.............................................. 232
FEADDR_REG-Fault Event Address Register ......................................... 232
FEUADDR_REG-Fault Event Upper Address Register.............................. 232
AFLOG_REG-Advanced Fault Log Register ........................................... 233
PMEN_REG-Protected Memory Enable Register..................................... 234
PLMBASE_REG-Protected Low-Memory Base Register ........................... 235
PLMLIMIT_REG-Protected Low-Memory Limit Register........................... 236
PHMBASE_REG-Protected High-Memory Base Register .......................... 237
PHMLIMIT_REG-Protected High-Memory Limit Register ......................... 238
IQH_REG-Invalidation Queue Head Register ........................................ 239
IQT_REG-Invalidation Queue Tail Register........................................... 239
IQA_REG-Invalidation Queue Address Register .................................... 240
ICS_REG-Invalidation Completion Status Register ................................ 240
IECTL_REG-Invalidation Event Control Register.................................... 241
IEDATA_REG-Invalidation Event Data Register..................................... 242
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