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Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - SPECIFICATION UPDATE 01-2011 Specification

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2nd Generation Intel
Core
Processor Family Desktop
Specification Update
January 2011
Reference Number: 324643-001

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  Summary of Contents for Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY DESKTOP - SPECIFICATION UPDATE 01-2011

  • Page 1 ® 2nd Generation Intel Core ™ Processor Family Desktop Specification Update January 2011 Reference Number: 324643-001...
  • Page 2 It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off.
  • Page 3: Table Of Contents

    Contents Contents Revision History ....................... 5 Preface ..........................6 Summary Tables of Changes ..................8 Identification Information ....................12 Errata ..........................14 Specification Changes....................37 Specification Clarifications ................... 38 Documentation Changes ....................39 § Specification Update...
  • Page 4 Contents Specification Update...
  • Page 5: Revision History

    Revision History Revision Description Date -001 Initial Release January 2011 Specification Update...
  • Page 6: Preface

    Volume 3A: System Programming Guide ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System Programming Guide ® Intel 64 and IA-32 Intel Architecture Optimization Reference Manual http://www.intel.com/ ® Intel 64 and IA-32 Architectures Software Developer’s Manual design/processor/ Documentation Changes specupdt/252046.htm...
  • Page 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products.
  • Page 8: Summary Tables Of Changes

    Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
  • Page 9 Errata (Sheet 2 of 4) Steppings Number Status ERRATA Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher No Fix Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack Corruption of CS Segment Register During RSM While Transitioning From Real No Fix Mode to Protected Mode Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled...
  • Page 10 Wraps a 64-Kbyte Boundary in 16-Bit Code BJ40 No Fix Spurious Interrupts May be Generated From the Intel® VT-d Remap Engine Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation BJ41 No Fix Descriptors VPHMINPOSUW Instruction in Vex Format Does Not Signal #UD When vex.vvvv...
  • Page 11 C-state Exit Latencies May be Higher Than Expected MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control BJ61 No Fix Offset Field Intel® VT-d Interrupt Remapping Will Not Report a Fault if Interrupt Index Exceeds BJ62 No Fix FFFFH BJ63 No Fix PCIe Link Speed May Not Change From 5.0 GT/s to 2.5 GT/s...
  • Page 12: Identification Information

    The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, ® or Intel Core™ processor family. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor’s family.
  • Page 13 Processor Production Top-side Markings (Example) ©'10 BRAND PROC# SLxxx SPEED [COO] [FPO] LOT NO S/N Table 1. Processor Identification (Sheet 1 of 2) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / SpecNu Stepping Technology L3 Cache...
  • Page 14 Trusted Execution Technology (Intel TXT) enabled. ® ® ® ® Intel Virtualization Technology for IA-32, Intel 64 and Intel Architecture (Intel VT-x) enabled. ® ® Intel Virtualization Technology for Directed I/O (Intel VT-d) enabled. ® Intel AES-NI enabled. Specification Update...
  • Page 15: Errata

    Workaround: As recommended in the IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of...
  • Page 16 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
  • Page 17 Developer's Manual Volume 3A: System Programming Guide, Part 1, in the section titled “Switching to Protected Mode” recommends the far JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software.
  • Page 18 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
  • Page 19 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially available software. Workaround:...
  • Page 20 BJ16. IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly Problem: The IO_SMI bit in SMRAM's location 7FA4H is set to “1” by the CPU to indicate a System Management Interrupt (SMI) occurred as the result of executing an instruction that reads from an I/O port.
  • Page 21 The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software. Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
  • Page 22 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
  • Page 23 • UC the data size of each write will now always be 8 bytes, as opposed to the original data size. • WP the data size of each write will now always be 8 bytes, as opposed to the original data size and there may be a memory ordering violation.
  • Page 24 Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.
  • Page 25: Byte Count

    Due to this erratum, the PCIe root port may not initiate a link speed change during some hardware scenarios causing the PCIe link to operate at a lower than expected speed. Intel has not observed this erratum with any commercially available platform. Workaround:...
  • Page 26 Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit FP load around a 4-Gbyte boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software. Workaround:...
  • Page 27 Upon detection of a non-zero bit in a reserved field an Intel VT-d fault should be recorded. Due to this erratum the processor does not check reserved bit values for Queued Invalidation descriptors.
  • Page 28 Unsupported Field in VMCS Problem: The Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B states that execution of VMREAD or VMWRITE should fail if the value of the instruction's register source operand corresponds to an unsupported field in the VMCS (Virtual Machine Control Structure).
  • Page 29 If this erratum occurs the system may have unpredictable behavior including a system hang. The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being unsupported in the Intel 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
  • Page 30 BJ48. PCI Express Graphics Receiver Error Reported When Receiver With L0s Enabled and Link Retrain Performed Problem: If the Processor PCI Express root port is the receiver with L0s enabled and the root port itself initiates a transition to the recovery state via the retrain link configuration bit in the 'Link Control' register (Bus 0;...
  • Page 31 If the processor throttles due to either high temperature thermal conditions or due to an explicit operating system throttling request (TT1) while executing GETSEC[SENTER] or GETSEC[SEXIT] instructions, then under certain circumstances, the processor may hang. Intel has not been observed this erratum with any commercially available software. Implication: Possible hang during execution of GETSEC instruction.
  • Page 32 Implication: Due to this erratum an unexpected machine check with error code 0150H may occur, possibly resulting in a shutdown. Intel has not observed this erratum with any commercially available software. Workaround: Software should not write to a paging-structure entry in a way that would change, for any linear address, both the page size and the memory type.
  • Page 33 Core C-state exit can be delayed if a P-state transition is requested before the pending C-state exit request is completed. Under certain internal conditions the core C-state exit latencies may be over twice the value specified in the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
  • Page 34 L1 power management mode is entered, further retrains initiated by software will not change speed to 2.5 GT/s. Implication: Intel has not observed any PCI Express device that changes supported link speed without actually initiating a speed change. Workaround: None identified.
  • Page 35 In this case, the store may cause a page fault or EPT violation that indicates that there is no translation for the page (e.g., with bit 0 clear in the page-fault error code, indicating that the fault was caused by a not-present page). Intel has not observed this erratum with any commercially available software.
  • Page 36 (TT1) while executing GETSEC[SENTER] or GETSEC[SEXIT] instructions, then under certain circumstances, the processor may hang. Implication: Possible hang during execution of GETSEC instruction. Intel has not been observed this erratum with any commercially available software. Workaround: None Identified.
  • Page 37: Branch Instructions

    BJ72. Unexpected #UD on VPEXTRD/VPINSRD Problem: Execution of the VPEXTRD or VPINSRD instructions outside of 64-bit mode with VEX.W set to 1 may erroneously cause a #UD (invalid-opcode exception). Implication: The affected instructions may produce unexpected invalid-opcode exceptions outside 64-bit mode. Workaround: Software should encode VEX.W = 0 for executions of the VPEXTRD and VPINSRD instructions outside 64-bit mode.
  • Page 38 BJ76. A Read from The APIC-Timer CCR May Disarm The TSC_Deadline Counter Problem: When in TSC Deadline mode with TSC_Deadline timer armed (IA32_TSC_DEADLINE<>0, MSR 6E0H), a read from the local APIC’s CCR (current count register) using RDMSR 0839H may disarm the TSC Deadline timer without generating an interrupt as specified in the APIC Timer LVT (Local Vector Table) entry.
  • Page 39: Specification Changes

    Specification Changes The Specification Changes listed in this section apply to the following documents: ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M ®...
  • Page 40: Specification Clarifications

    Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M ®...
  • Page 41: Documentation Changes

    All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation. ® Note: Documentation changes for Intel 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate ®...

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