Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 257

Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
13:8
7:6
5:0
Datasheet, Volume 2
0/0/0/MCHBAR PCU
5D10–5D17h
0000000000000000h
RWS
64 bits
Reset RST/
Attr
Value PWR
Powerg
RWS 000000b
ood
Powerg
RWS 00b
ood
Powerg
RWS 000000b
ood
Description
Self Refresh Latency Time (WM1)
Number of microseconds to access memory if memory is in Self
Refresh (0.5 us granularity).
00h = 0 us
01h = 0.5 us
02h = 1 us
...
3Fh = 31.5 us
NOTE: The value in this field corresponds to the memory latency
requested to the Display Engine when Memory is in Self Refresh.
The Display LP1 latency and watermark values (GTTMMADR offset
45118h) should be programmed to match the latency in this
register.
Reserved for Future Use (RWSVD0)
Normal Latency Time (WM0)
Number of microseconds to access memory for normal memory
operations (0.1 us granularity).
00h = 0 us
01h = 0.1 us
02h = 0.2 us
...
3Fh = 6.3 us
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