Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 61

Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:39
38:28
27
26
25:3
2:1
0
Datasheet, Volume 2
0/0/0/PCI
60–67h
0000000000000000h
RW, RW-V
64 bits
000000000000h
Reset RST/
Attr
Value PWR
RO 0h
RW 000h Uncore
RW-V 0b Uncore
RW-V 0b Uncore
RO 0h
RW 00b Uncore
RW 0b Uncore
Description
Reserved
PCI Express Base Address (PCIEXBAR)
This field corresponds to bits 38:28 of the base address for PCI
Express enhanced configuration space. BIOS will program this
register resulting in a base address for a contiguous memory
address space. The size of the range is defined by bits 2:1 of this
register.
This base address shall be assigned on a boundary consistent with
the number of buses (defined by the Length field in this register)
above TOLUD and still within the 39-bit addressable memory
space. The address bits decoded depend on the length of the
region defined by this register.
This register is locked by Intel TXT.
The address used to access the PCI Express configuration space for
a specific device can be determined as follows:
PCI Express Base Address + Bus Number * 1MB + Device
Number * 32KB + Function Number * 4KB
This address is the beginning of the 4 KB space that contains both
the PCI compatible configuration space and the PCI Express
extended configuration space.
128MB Base Address Mask (ADMSK128)
This bit is either part of the PCI Express Base Address (RW) or part
of the Address Mask (RO, read 0b), depending on the value of bits
[2:1] in this register.
64MB Base Address Mask (ADMSK64)
This bit is either part of the PCI Express Base Address (RW) or part
of the Address Mask (RO, read 0b), depending on the value of bits
[2:1] in this register.
Reserved
Length (LENGTH)
This field describes the length of this region.
00 = 256 MB (buses 0–255). Bits 38:28 are decoded in the PCI
Express Base Address field.
01 = 128 MB (buses 0–127). Bits 38:27 are decoded in the PCI
Express Base Address field.
10 = 64 MB (buses 0–63). Bits 38:26 are decoded in the PCI
Express Base Address field.
11 = Reserved.
This register is locked by Intel TXT.
PCIEXBAR Enable (PCIEXBAREN)
0 = The PCIEXBAR register is disabled. Memory read and write
transactions proceed as if there were no PCIEXBAR register.
PCIEXBAR bits 38:26 are RW with no functionality behind
them.
1 = The PCIEXBAR register is enabled. Memory read and write
transactions whose address bits 38:26 match PCIEXBAR will
be translated to configuration reads and writes within the
Uncore. These translated cycles are routed as shown in the
above table.
This register is locked by Intel TXT.
61