Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 224

B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
25
24
23
22:0
224
0/0/0/GFXVTBAR
18–1Bh
00000000h
RO, WO
32 bits
000000h
Reset RST/
Attr
Value PWR
WO 0b Uncore
WO 0b Uncore
WO 0b Uncore
RO 0h
Processor Configuration Registers
Description
Interrupt Remapping Enable (IRE)
This field is valid only for implementations supporting interrupt
remapping.
0 = Disable interrupt-remapping hardware
1 = Enable interrupt-remapping hardware
Hardware reports the status of the interrupt remapping enable
operation through the IRES field in the Global Status register.
There may be active interrupt requests in the platform when
software updates this field. Hardware must enable or disable
interrupt-remapping logic only at deterministic transaction
boundaries, so that any in-flight interrupts are either subject to
remapping or not at all.
Hardware implementations must drain any in-flight interrupt
requests queued in the Root-Complex before completing the
interrupt-remapping enable command and reflecting the status of
the command through the IRES field in the Global Status register.
The value returned on a read of this field is undefined.
Set Interrupt Remap Table Pointer (SIRTP)
This field is valid only for implementations supporting interrupt-
remapping.
Software sets this field to set/update the interrupt remapping table
pointer used by hardware. The interrupt remapping table pointer is
specified through the Interrupt Remapping Table Address
(IRTA_REG) register.
Hardware reports the status of the 'Set Interrupt Remap Table
Pointer' operation through the IRTPS field in the Global Status
register.
The 'Set Interrupt Remap Table Pointer' operation must be
performed before enabling or re-enabling (after disabling)
interrupt-remapping hardware through the IRE field.
After a 'Set Interrupt Remap Table Pointer' operation, software
must globally invalidate the interrupt entry cache. This is required
to ensure hardware uses only the interrupt-remapping entries
referenced by the new interrupt remap table pointer, and not any
stale cached entries.
While interrupt remapping is active, software may update the
interrupt remapping table pointer through this field. However, to
ensure valid in-flight interrupt requests are deterministically
remapped, software must ensure that the structures referenced by
the new interrupt remap table pointer are programmed to provide
the same remapping results as the structures referenced by the
previous interrupt remap table pointer.
Clearing this bit has no effect. The value returned on a read of this
field is undefined.
Compatibility Format Interrupt (CFI)
This field is valid only for Intel 64 implementations supporting
interrupt-remapping.
Software writes to this field to enable or disable Compatibility
Format interrupts on Intel 64 platforms. The value in this field is
effective only when interrupt-remapping is enabled and Extended
Interrupt Mode (x2APIC mode) is not enabled.
0 = Block Compatibility format interrupts.
1 = Process Compatibility format interrupts as pass-through
(bypass interrupt remapping).
Hardware reports the status of updating this field through the CFIS
field in the Global Status register.
The value returned on a read of this field is undefined.
Reserved
Datasheet, Volume 2