Dsts - Device Status; Dsts - Device Status Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Table 59. DCTL - Device Control Register (Sheet 2 of 2)
Default
Bit Access
Value
1 RW
0 RW
6.2.37

DSTS - Device Status

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Reflects status corresponding to controls in the Device Control register. The error
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
Table 60.

DSTS - Device Status Register

Bit Access
15:6 RO
5 RO
4 RO
3 RWC
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
114
RST/
PWR
0b Core Non-Fatal Error Reporting Enable (NERE)
When set, enables signaling of ERR_NONFATAL to the Root
Control register due to internally detected errors or error
messages received across the link. Other bits also control the full
scope of related error reporting.
0b Core Correctable Error Reporting Enable (CERE)
When set, enables signaling of ERR_CORR to the Root Control
register due to internally detected errors or error messages
received across the link. Other bits also control the full scope of
related error reporting.
Default RST/
Value PWR
000h Core
0b Core
0b Core
0b Core
®
Celeron
Description
0/6/0/PCI
AA-ABh
0000h
RO; RWC
16 bits
Description
Reserved and Zero (RSVD)
For future R/WC/S implementations; software must use 0
for writes to bits.
Transactions Pending (TP)
0 = All pending transactions (including completions for
any outstanding non-posted requests on any used
virtual channel) have been completed.
1 = Indicates that the device has transaction(s) pending
(including completions for any outstanding non-
posted requests for all used Traffic Classes).
Reserved
Unsupported Request Detected (URD)
When set this bit indicates that the Device received an
Unsupported Request. Errors are logged in this register
regardless of whether error reporting is enabled or not in
the Device Control Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal
Error Detected bit is set according to the setting of the
Unsupported Request Error Severity bit. In production
systems setting the Fatal Error Detected bit is not an
option as support for AER will not be reported.
®
Processor P4500, P4505 Series
Processor Configuration Registers
April 2010
Document Number: 323178-002