ST STM32F405 Reference Manual page 1192

Ethernet (ETH): media access control (MAC) with DMA controller
Bits 19:17 IFG: Interframe gap
These bits control the minimum interframe gap between frames during transmission.
Note: In Half-duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100)
Bit 16 CSD: Carrier sense disable
Bit 15 Reserved, must be kept at reset value.
Bit 14 FES: Fast Ethernet speed
Bit 13 ROD: Receive own disable
Bit 12 LM: Loopback mode
Bit 11 DM: Duplex mode
Bit 10 IPCO: IPv4 checksum offload
Bit 9 RD: Retry disable
Note: This bit is applicable only in the Half-duplex mode.
Bit 8 Reserved, must be kept at reset value.
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000: 96 bit times
001: 88 bit times
010: 80 bit times
....
111: 40 bit times
only. Lower values are not considered.
When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame
transmission in Half-duplex mode. No error is generated due to Loss of Carrier or No Carrier
during such transmission.
When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and
even aborts the transmissions.
Indicates the speed in Fast Ethernet (MII) mode:
0: 10 Mbit/s
1: 100 Mbit/s
When this bit is set, the MAC disables the reception of frames in Half-duplex mode.
When this bit is reset, the MAC receives all packets that are given by the PHY while
transmitting.
This bit is not applicable if the MAC is operating in Full-duplex mode.
When this bit is set, the MAC operates in loopback mode at the MII. The MII receive clock
input (RX_CLK) is required for the loopback to work properly, as the transmit clock is not
looped-back internally.
When this bit is set, the MAC operates in a Full-duplex mode where it can transmit and
receive simultaneously.
When set, this bit enables IPv4 checksum checking for received frame payloads'
TCP/UDP/ICMP headers. When this bit is reset, the checksum offload function in the
receiver is disabled and the corresponding PCE and IP HCE status bits (see
always cleared.
When this bit is set, the MAC attempts only 1 transmission. When a collision occurs on the
MII, the MAC ignores the current frame transmission and reports a Frame Abort with
excessive collision error in the transmit frame status.
When this bit is reset, the MAC attempts retries based on the settings of BL.
RM0090 Rev 18
RM0090
Table 190) are