Uart Reception - NEC 78K0R/KE3 User Manual

11.6.2 UART reception

UART reception is an operation wherein the 78K0R/KE3 asynchronously receives data from another device (start-
stop synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of
both the odd- and even-numbered channels must be set.
UART
Target channel Channel 1 of SAU0
Pins used RxD0
Interrupt INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt INTSRE0
• Framing error detection flag (FEFmn)
Error detection flag
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
Transfer data length 5, 7 or 8 bits
Transfer rate Max. f
Data phase Forward output (default: high level)
Reverse output (default: low level)
Parity bit The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Stop bit Appending 1 bit
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 27
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remarks 1. f : Operation clock (MCK) frequency of target channel
MCK
f : System clock frequency
CLK
2. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 13
430
CHAPTER 11 SERIAL ARRAY UNIT
UART0
Channel 3 of SAU0
RxD1
INTSR1
INTSRE1
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
MCK
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
User's Manual U17854EJ9V0UD
UART1
Channel 3 of SAU1
RxD3
INTSR3
INTSRE3
/(2 × 2 × 128) [bps]
Note
11
CLK
UART3