16-Bit Timer/Event Counter Operating Precautions - NEC mPD780065 Series Preliminary User's Manual

6.6 16-Bit Timer/Event Counter Operating Precautions

(1) Timer start errors
An error with a maximum of one clock may occur concerning the time required for a match signal to be generated
after timer start. This is because 16-bit timer/counter 0 (TM0) is started asynchronously with the count pulse.
Count pulse
TM0 count value
(2) 16-Bit Compare Register Setting
Set other than 0000H to 16-bit timer capture/compare registers 00, 01 (CR00, CR01). This means 1-pulse count
operation cannot be performed when it is used as the event counter.
(3) Operation after compare register change during timer count operation
If the value after 16-bit timer capture/compare register 00 (CR00) is changed is smaller than that of 16-bit timer/
counter 0 (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M)
after CR00 change is smaller than that (N) before change, it is necessary to restart the timer after changing CR00.
Figure 6-29. Timings after Change of Compare Register during Timer Count Operation
Count pulse
CR00
TM0 count value
Remark N > X > M
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER
Figure 6-28. 16-Bit Timer/Counter 0 (TM0) Start Timing
0000H 0001H
Timer start
N
X–1 X
Preliminary User's Manual U13420EJ2V0UM00
0002H 0003H 0004H
M
FFFFH 0000H 0001H 0002H