Block Transfer Mode; Transfer Types; Two-Cycle Transfer - NEC PD703114 User Manual

6.4.3 Block transfer mode

In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the
bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer.
After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged.
The following shows an example of block transfer in which a higher priority DMA request is issued. DMA channels
2 and 3 are in the block transfer mode.
DMARQ2
(internal signal)
DMARQ3
(internal signal)
CPU CPU CPU DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 CPU DMA2 DMA2 DMA2 DMA2 DMA2

6.5 Transfer Types

6.5.1 Two-cycle transfer

In two-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle
(DMAC to destination).
In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the
second cycle, the destination address is output and writing is performed from the DMAC to the destination.
Caution An idle cycle of 1 to 2 clocks is always inserted between the read cycle and write cycle.
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-7. Block Transfer Example
User's Manual U15195EJ5V0UD
DMA channel 3 terminal count
The bus is always
released.
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