ST STM32F446 Series Reference Manual page 1321

RM0390
Date
04-Jul-2017
Table 254. Document revision history (continued)
Revision
Added Section 28.3.2: SAI pins and internal signals
Section 1.4.9: SAI clock
Section 28.5.1: Global configuration register
Configuration register 1 (SAI_ACR1 /
Updated Figure 354: SAI functional block diagram
block clock generator
Updated Table 174: Example of possible audio frequency sampling range
and Table 178: SAI interrupt
Updated Section 31.1:
features, Section 31.9: OTG low-power
RAM allocation,
(OTG_GOTGCTL),
(OTG_GAHBCFG),
(OTG_GUSBCFG),
(OTG_GRSTCTL),
(OTG_GINTSTS),
(OTG_GRXFSIZ),
FIFO/queue status register
general core configuration register
OTG device IN endpoint transmit FIFO size register (OTG_DIEPTXFx)
(x = 1..5[FS] /8[HS], where x is the FIFO
device OUT endpoint common interrupt mask register
Section 31.15.48: OTG device IN endpoint x control register
(OTG_DIEPCTLx) (x = 1..5[FS] / 0..8[HS], where x = endpoint
3
Section 31.15.58: OTG device OUT endpoint x control register
cont'd
(OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = endpoint
Section 31.15.49: OTG device IN endpoint x interrupt register
(OTG_DIEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint
Section 31.15.55: OTG device OUT endpoint x interrupt register
(OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint
Section 31.15.53: OTG device IN endpoint x transfer size register
(OTG_DIEPTSIZx) (x = 1..5[FS] /8[HS], where x = endpoint
Section 31.15.52: OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where x = endpoint
Section 31.15.59: OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint
Section 31.16.3: Device
Section 31.16.5: Host programming model
programming
Added Section 31.15.14: OTG core LPM configuration register
(OTG_GLPMCFG)
address register (OTG_DIEPDMAx) (x = 0..8, where x = endpoint
Added Table 216: OTG_HS speeds supported
speeds supported.
Updated Table 223: Core global control and status registers
Table 225: Device-mode control and status registers
OTG_FS/OTG_HS register map and reset
Updated Section 32.1:
Added Section 32.3.2: HDMI-CEC block
RM0390 Rev 4
Changes
generator, Section 28.3.9: Internal
overview.
sources.
Introduction, Section 31.2.3: Peripheral-mode
Section 31.15.1: OTG control and status register
Section 31.15.3: OTG AHB configuration register
Section 31.15.4: OTG USB configuration register
Section 31.15.5: OTG reset register
Section 31.15.6: OTG core interrupt register
Section 31.15.9: OTG receive FIFO size register
Section 31.15.11: OTG non-periodic transmit
(OTG_HNPTXSTS),
(OTG_GCCFG),
initialization, Section 31.16.4: DMA
model.
and Section 31.15.51: OTG device IN endpoint x DMA
Introduction.
Revision history
and updated
FIFOs,
(SAI_GCR), Section 28.5.2:
SAI_BCR1).
and Figure 360: Audio
modes, Section 31.11.3: FIFO
Section 31.15.12: OTG
Section 31.15.16:
number), Section 31.15.36: OTG
(OTG_DOEPMSK),
number),
number),
number),
number),
number),
number),
mode,
and Section 31.16.6: Device
and Table 217: OTG_FS
(CSRs),
and Table 231:
values.
diagram.
number),
number).
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