Otg Device Status Register (Otg_Dsts) - ST STM32F446 Series Reference Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)

31.15.34 OTG device status register (OTG_DSTS)

Address offset: 0x808
Reset value: 0x0000 0010
This register indicates the status of the core with respect to USB-related events. It must be
read on interrupts from the device all interrupts (OTG_DAINT) register.
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:22 DEVLNSTS[1:0]: Device line status
Indicates the current logic level USB data lines.
Bit [23]: Logic level of D+
Bit [22]: Logic level of D-
Bits 21:8 FNSOF[13:0]: Frame number of the received SOF
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 EERR: Erratic error
The core sets this bit to report any erratic errors.
Due to erratic errors, the OTG_FS/OTG_HS controller goes into suspended state and an
interrupt is generated to the application with Early suspend bit of the OTG_GINTSTS register
(ESUSP bit in OTG_GINTSTS). If the early suspend is asserted due to an erratic error, the
application can only perform a soft disconnect recover.
Bits 2:1 ENUMSPD: Enumerated speed
Indicates the speed at which the OTG_FS/OTG_HS controller has come up after speed
detection through a chirp sequence.
01: Reserved
10: Reserved
11: Full speed (PHY clock is running at 48 MHz)
Others: reserved
Bit 0 SUSPSTS: Suspend status
In device mode, this bit is set as long as a suspend condition is detected on the USB. The
core enters the suspended state when there is no activity on the USB data lines for a period
of 3 ms. The core comes out of the suspend:
– When there is an activity on the USB data lines
– When the application writes to the remote wakeup signaling bit in the OTG_DCTL register
(RWUSIG bit in OTG_DCTL).
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28 27 26 25
Res. Res. Res.
12 11 10 9
FNSOF[7:0]
r r r r
24 23 22
Res. DEVLNSTS[1:0]
r
8 7 6
Res. Res.
r
RM0390 Rev 4
21 20 19 18
FNSOF[13:8]
r r r r
5 4 3 2
Res. Res. EERR ENUMSPD
r r
RM0390
17 16
r r
1 0
SUSP
STS
r r