31.15.35 Otg Device In Endpoint Common Interrupt Mask Register; (Otg_Diepmsk) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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31.15.35 OTG device IN endpoint common interrupt mask register

Address offset: 0x810

Reset value: 0x0000 0000

This register works with each of the OTG_DIEPINTx registers for all endpoints to generate

an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the

OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register.

Status bits are masked by default.

Configuration register for USB OTG FS

Configuration register for USB OTG HS

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NAKM: NAK interrupt mask

Bits 12:10 Reserved, must be kept at reset value.

Bit 9 Reserved, must be kept at reset value.

Bit 8 TXFURM: FIFO underrun mask

Bit 7 Reserved, must be kept at reset value.

Bit 6 INEPNEM: IN endpoint NAK effective mask

Bit 5 INEPNMM: IN token received with EP mismatch mask

0: Masked interrupt

1: Unmasked interrupt

0: Masked interrupt

1: Unmasked interrupt

0: Masked interrupt

1: Unmasked interrupt

0: Masked interrupt

1: Unmasked interrupt

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)

RM0390 Rev 4

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