Otg Power And Clock Gating Control Register (Otg_Pcgcctl) - ST STM32F446 Series Reference Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
STUPCNT[1:0]: SETUP packet count
Bits 28:19 PKTCNT: Packet count
Bits 18:0 XFRSIZ: Transfer size

31.15.60 OTG power and clock gating control register (OTG_PCGCCTL)

Address offset: 0xE00
Reset value: 0x200B 8000
This register is available in host and device modes.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 SUSP: Deep Sleep
Bit 6 PHYSLEEP: PHY in Sleep
Bit 5 ENL1GTG: Enable sleep clock gating
Bit 4 PHYSUSP: PHY suspended
1190/1328
Applies to control OUT endpoints only.
This field specifies the number of back-to-back SETUP data packets the endpoint can
receive.
01: 1 packet
10: 2 packets
11: 3 packets
Indicates the total number of USB packets that constitute the transfer size amount of data for
this endpoint.
This field is decremented every time a packet (maximum size or short packet) is written to
the Rx FIFO.
This field contains the transfer size in bytes for the current endpoint. The core only interrupts
the application after it has exhausted the transfer size amount of data. The transfer size can
be set to the maximum packet size of the endpoint, to be interrupted at the end of each
packet.
The core decrements this field every time a packet is read from the Rx FIFO and written to
the external memory.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit indicates that the PHY is in Deep Sleep when in L1 state.
This bit indicates that the PHY is in the Sleep state.
When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot
assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep
state.
Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended
after the application has set the STPPCLK bit.
24 23 22
Res. Res. Res.
8 7 6
PHY ENL1
Res. SUSP
SLEEP
r r
RM0390 Rev 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PHY
Res. Res.
GTG SUSP
r
rw
RM0390
17 16
Res. Res.
1 0
GATE STPP
HCLK CLK
rw rw