ST STM32F446 Series Reference Manual page 1320

Revision history
Date
04-Jul-2017
1320/1328
Table 254. Document revision history (continued)
Revision
Updated Section 1.1: List of abbreviations for
Updated Section 5.4.2: PWR power control/status register
Replaced former
DMA block diagram
Updated Section 11.1: FMC main
timing registers 1..4
register 2..4 (FMC_PMEM),
(FMC_PATT)
Updated Table 54: FMC_BCRx bit fields
fields.
Updated Figure 39: Mode2 write access waveforms
Flash controller waveforms for common memory
Added Section 12.3.2: QUADSPI
Updated Section 12.3.7: QUADSPI memory-mapped
Section 12.3.13: QUADSPI error management
QUADSPI control register
Updated notes in
(ADC_HTR)
(ADC_LTR).
Removed former
DCMI block diagram.
3
Updated Table 96: DCMI external
Changed D, PIXCLK, HSYNC and VSYNC with, respectively, DCMI_D,
DCMI_HSYNC, DCMI_VSYNC and DCMI_VSYNC in
camera interface
Updated FMPI2C master
(FMPI2C_CR2),
Section 23.7.4: Own address 2 register (FMPI2C_OAR2)
Section 23.7.5: Timing register
Updated Figure 247: Slave initialization
Updated Section 25.6.1: Status register
Updated Section 26.1:
notes in Resetting the SPIx_TXCRC and SPIx_RXCRC values
Section 26.7.1: SPI control register 1 (SPI_CR1) (not used in I2S
Added Section 26.6.2: I2S
Updated Section 27.2: SPDIFRX main
functional description,
Section 27.5.3: Status register
Added Section 56.3.11: Symbol clock
Interface, Section 56.5.10: SPDIFRX version register
Section 56.5.11: SPDIFRX identification register (SPDIFRX_IPIDR)
Section 56.5.12: SPDIFRX size identification register
Updated Table 170: SPDIFRX interface register map and reset
RM0390 Rev 4
Changes
Section 9.3.1: General description
and Section 9.3.1: DMA block
features,
(FMC_BTR1..4),
Attribute memory space timing registers
and SDRAM Control registers 1,2
pins.
(QUADSPI_CR).
Section 13.13.7: ADC watchdog higher threshold register
and Section 13.13.8: ADC watchdog lower threshold register
Section 15.3: DCMI pins
signals.
(DCMI).
initialization,
Section 23.7.3: Own address 1 register
(FMPI2C_TIMINGR).
Introduction, Section 26.3.7: SPI configuration
full-duplex.
Section 27.5.1: Control register (SPDIFRX_CR)
(SPDIFRX_SR).
registers.
(PWR_CSR).
with Section 9.3.1:
diagram.
SRAM/NOR-Flash chip-select
Common memory space timing
(FMC_SDCR1,2).
and Table 72: FMC_BCRx bit
and Figure 52: NAND
access.
mode,
and Section 12.5.1:
and added Section 15.4.1:
Section 15: Digital
Section 23.7.2: Control register 2
(FMPI2C_OAR1),
and
flowchart.
(USART_SR).
features, Section 27.3: SPDIFRX
generation, Section 27.3.10: DMA
(SPDIFRX_VERR),
(SPDIFRX_SIDR).
RM0390
and
and in
mode).
and
and
values.