Revision History; Table 254. Document Revision History - ST STM32F446 Series Reference Manual

RM0390
35

Revision history

Date
17-Mar-2015
12-Jan-2016

Table 254. Document revision history

Revision
1 Initial release.
Updated Section 5.1.2: Battery backup
Updated Table 19: Standby mode entry and
Updated Section 6.3.2: RCC PLL configuration register
Section 6.3.23: RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
and Section 6.3.24: RCC PLL configuration register
Updated Section 11.3: AHB
mapping, Section 11.5.4: NOR Flash/PSRAM controller asynchronous
transactions,
SRAM/NOR-Flash write timing registers 1..4
status and interrupt register
register 2..4 (FMC_PMEM)
(FMC_PATT),
Updated Table 74: Programmable NAND Flash access
Updated figures 32, 43, 44,
Updated footnote
footnote 1 to
Updated Section 12.5.7: QUADSPI address register
Updated Section 13.2: ADC main features
control register 1
Updated figures 110,
Updated Figure
(TIMx_SMCR)
2
Updated Table 115: TIMx internal trigger connections
mode in Section
Updated Figure 238: Watchdog block diagram
program the watchdog
Updated Section 22.6.4: RTC initialization and status register
Updated Section 23.7.5: Timing register
Updated Section 24.6.2: I2C Control register 2
Added Section 25.3: USART
Updated tables in
Updated figures 305, 306,
Section 26.3: SPI functional
Updated Section 29.1: SDIO main
description, Section 29.8.1: SDIO power control register
Section 29.8.2: SDIO clock control register (SDIO_CLKCR)
Section 29.8.4: SDIO command register
Updated Section 30.7.4: Identifier
(CAN_FM1R),
assignment register
(CAN_FA1R)
Updated Section 31.15.5: OTG reset register
Updated Section 33.6.1: MCU device ID code
Cortex®-M4 with FPU
RM0390 Rev 4
Changes
interface,
Section 11.5.6: NOR/PSRAM controller
(FMC_SR),
and Attribute memory space timing registers
SDRAM initialization.
45 and 46
5 of Figure 53, and added footnote
Figure 91.
(ADC_CR1).
139, 153 and Input capture mode
183, Section 17.4.3: TIMx slave mode control register
and Input capture mode
18.
timeout.
implementation.
Section 25.4.4: Fractional baud rate
307 and 308, and their footnotes in
description.
features,
filtering,
CAN filter scale register
(CAN_FFA1R), CAN filter activation register
and Section 30.9.5: bxCAN register
TAP.
Revision history
domain.
exit.
(RCC_PLLCFGR),
(RCC_PLLSAICFGR).
Section 11.4.3: SDRAM address
registers,
(FMC_BWTR1..4),
Common memory space timing
parameters.
in Section 11.
2 to Figure 52
(QUADSPI_AR).
and Section 13.13.2: ADC
in Section
in Section 17.
and Input capture
and Section 21.4: How to
(RTC_ISR).
(FMPI2C_TIMINGR).
(I2C_CR2).
generation.
Section 29.3: SDIO functional
(SDIO_POWER),
and
(SDIO_CMD).
CAN filter mode register
(CAN_FS1R), CAN filter FIFO
map.
(OTG_GRSTCTL).
and Section 33.6.3:
FIFO
and
16.
1319/1328
1323