Otg Device Threshold Control Register (Otg_Dthrctl) - ST STM32F446 Series Reference Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DVBUSP[11:0]: Device V

31.15.41 OTG device threshold control register (OTG_DTHRCTL)

Address offset: 0x0830
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 ARPEN: Arbiter parking enable
Bit 26
Bits 25: 17 RXTHRLEN[8:0]: Receive threshold length
Bit 16 RXTHREN: Receive threshold enable
Bits 15: 11
1168/1328
BUS
Specifies the V pulsing time during SRP. This value equals:
BUS
V pulsing time in PHY clocks / 1 024
BUS
28 27 26 25
ARPEN Res.
rw rw
12 11 10 9
Res.
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This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled
and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token
received on the USB. This is done to avoid getting into underrun conditions. By default
parking is enabled.
Reserved, must be kept at reset value.
This field specifies the receive thresholding size in 32-bit words. This field also specifies the
amount of data received on the USB before the core can start transmitting on the AHB. The
threshold length has to be at least eight 32-bit words. The recommended value for
RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in
OTG_GAHBCFG).
When this bit is set, the core enables thresholding in the receive direction.
Reserved, must be kept at reset value.
pulsing time. This feature is only relevant to OTG1.3.
24 23 22
RXTHRLEN[8:0]
rw rw rw
8 7 6
TXTHRLEN[8:0]
rw rw rw
RM0390 Rev 4
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0390
17 16
RXTH
REN
rw rw
1 0
NONIS
ISOT
OTH
HREN
REN
rw rw