ST STM32F446 Series Reference Manual page 1322

Revision history
Date
12-Feb-2018
1322/1328
Table 254. Document revision history (continued)
Revision
Updated Introduction
Updated Section 2.2.1: Introduction
register boundary
Updated Section 5.4.2: PWR power control/status register
Updated Section 9.1: DMA
Updated Section 12.5.4: QUADSPI flag clear register
Updated Section 15.7.6: DCMI interrupt clear register
Updated Section 23.2: FMPI2C main
block diagram,
FMPI2C interrupts
Updated Table 127: STM32F446xx FMPI2C implementation
Figure 241: FMPI2C block
Added Table 132: Examples of timings settings for fI2CCLK = 16 MHz
Table 131: Examples of timing settings for fI2CCLK = 8
Updated Section 26.1: Introduction
Updated Section 27.3: SPDIFRX functional
Data reception management
(SPDIFRX_CR).
Removed former
Section 56.5.10: SPDIFRX version register
Section 56.5.11: SPDIFRX identification register (SPDIFRX_IPIDR)
Section 56.5.12: SPDIFRX size identification register
Updated Table 170: SPDIFRX interface register map and reset
4
Updated Frame synchronization
SPDIF generator
(AFSDET), Wrong clock configuration in master mode (with NODIV =
Section 28.3.14: Disabling the SAI
register 1 (SAI_ACR1 /
Updated Table 171: SAI internal input/output
input/output pins
Updated Section 30.2: bxCAN main
filters, Section 30.6: Behavior in debug mode
filter registers.
Updated Figure 394: Filtering mechanism -
and Figure 398: Event flags and interrupt
Updated Figure 400: OTG full-speed block
high-speed block
(RLDCTRL =
Updated Table 223: Core global control and status registers
Table 224: Host-mode control and status registers
Device-mode control and status
gating control and status
map and reset
Removed former
I2C interface,
(OTG_GI2CCTL)
Added Table 218: OTG implementation for
OTG_FS input/output pins
RM0390 Rev 4
Changes
and Section 1.1: List of abbreviations for
and
addresses, and added
introduction,
features,
Section 23.4.10: SMBus specific
and Section 23.7.9: PEC register
diagram.
and
and Section 27.5.1: Control register
Section 27.3.10: Symbol clock
polarity,
mode, Anticipated frame synchronization detection
and
SAI_BCR1).
and Table 179: SAI register map and reset
features,
diagram, Figure 406: Updating OTG_HFIR dynamically
0), Figure 409: Interrupt hierarchy
registers,
registers, Table 231: OTG_FS/OTG_HS register
values.
Section 31.4.6: External Full-speed OTG PHY using the
Section 31.15.12: OTG I2C access register
and former footnote
and Table 220: OTG_HS input/output
Section 2.2.2: Memory map and
Figure 2: Memory map.
(PWR_CSR).
Section 9.2: DMA main
(QUADSPI_FCR).
(DCMI_ICR).
Section 23.4.1: FMPI2C
features, Section 23.6:
(FMPI2C_PECR).
and
MHz.
Section 26.1: Introduction.
description, Section 27.3.6:
generation,
(SPDIFRX_VERR),
(SPDIFRX_SIDR).
Clock generator programming in
Section 28.5.2: Configuration
signals, Table 172: SAI
values.
Section 30.3.4: Acceptance
and Section 30.9.4: CAN
example, Figure 396: Bit timing
generation.
diagram, Figure 401: OTG
and its footnote.
(CSRs),
(CSRs), Table 225:
Table 227: Power and clock
1 from Figure 404.
STM32F446xx, Table 219:
RM0390
registers.
features.
and
and
values.
0),
pins.