Otg Core Id Register (Otg_Cid); Otg Core Lpm Configuration Register (Otg_Glpmcfg) - ST STM32F446 Series Reference Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
Bit 18 Reserved, must be kept at reset value.
Bit 17 Reserved, must be kept at reset value.
Bit 16 PWRDWN: Power down control
Used to activate the transceiver in transmission/reception. When reset, the transceiver is
kept in power-down. 0 = USB FS transceiver disabled
1 = USB FS transceiver enabled
Bits 15:4 Reserved, must be kept at reset value.
Bits 3:1 Reserved, must be kept at reset value.
Bits 0 Reserved, must be kept at reset value.

31.15.13 OTG core ID register (OTG_CID)

Address offset: 0x03C
Reset value: 0x0000 2000 for USB OTG FS
Reset value: 0x0000 2100 for USB OTG HS
This is a register containing the Product ID as reset value.
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 PRODUCT_ID: Product ID field

31.15.14 OTG core LPM configuration register (OTG_GLPMCFG)

Address offset: 0x54
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
BESL
15 14 13
SLP L1DS
LPMRSP[1:0]
STS
r r r
1138/1328
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Application-programmable ID field.
28 27 26 25
EN
LPMRCNTSTS[2:0]
rw r r r
12 11 10 9
BESLTHRS[3:0]
EN
rw rw rw rw
24 23 22
PRODUCT_ID[31:16]
rw rw rw
8 7 6
PRODUCT_ID[15:0]
rw rw rw
24 23 22
SND
LPMRCNT[2:0]
LPM
rs rw rw
8 7 6
L1SS REM
EN WAKE
rw rw rw/r
RM0390 Rev 4
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
LPMCHIDX[3:0]
rw rw rw rw
5 4 3 2
BESL[3:0]
rw/r rw/r rw/r rw/r
RM0390
17 16
rw rw
1 0
rw rw
17 16
L1RSM
OK
rw r
1 0
LPM LPM
ACK EN
rw rw