Table 251. Flexible Trace Pin Assignment - ST STM32F446 Series Reference Manual

Debug support (DBG)
This register is mapped on the external PPB and is reset by the PORESET (and not by the
SYSTEM reset). It can be written by the debugger under SYSTEM reset.
DBGMCU_CR
register
assigned
TRACE
TRACE
_MODE
_IOEN
[1:0]
No Trace
0 XX
(default state)
Asynchronous
1 00
Synchronous
1 01
Trace 1 bit
Synchronous
1 10
Trace 2 bit
Synchronous
1 11
Trace 4 bit
1. Refer to the Alternate function mapping table in the datasheets.
2. When Serial Wire mode is used, it is released. But when JTAG is used, it is assigned to JTDO.
Note: By default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK
two clock cycles after the bit TRACE_IOEN has been set.
The debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the
SPP_R (Selected Pin Protocol) register of the TPIU.
•
PROTOCOL=00: Trace Port Mode (synchronous)
•
PROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode).
Default state is 01
It then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R
(Current Sync Port Size Register) of the TPIU:
•
0x1 for 1 pin (default state)
• 0x2 for 2 pins
•
0x8 for 4 pins
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Table 251. Flexible TRACE pin assignment

Pins
PB3 /JTDO/
for:
TRACESWO
(2)
Released
TRACESWO
Trace
(2)
Released
TRACE IO pin assigned
PE2/
TRACED[0]
(1)
TRACECK
- -
TRACECK TRACED[0]
TRACECK TRACED[0] TRACED[1]
TRACECK TRACED[0] TRACED[1] TRACED[2] TRACED[3]
RM0390 Rev 4
TRACED[1] TRACED[2]
(1) (1)
-
Released
(usable as GPIO)
- -
-
RM0390
TRACED[3]
(1)
-
-