Otg General Core Configuration Register (Otg_Gccfg) - ST STM32F446 Series Reference Manual

RM0390
Bit 31 Reserved, must be kept at reset value.
Bits 30:24 NPTXQTOP[6:0]: Top of the non-periodic transmit request queue
Bits 23:16 NPTQXSAV[7:0]: Non-periodic transmit request queue space available
Bits 15:0 NPTXFSAV[15:0]: Non-periodic Tx FIFO space available

31.15.12 OTG general core configuration register (OTG_GCCFG)

Address offset: 0x038
Reset value: 0x0000 XXXX
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 VBDEN: USB V
Enables V
host and device operation. If HNP and/or SRP support is enabled, V
automatically enabled independently of VBDEN value.
0 = V
1 = V
Bits 20:19 Reserved, must be kept at reset value.
Entry in the non-periodic Tx request queue that is currently being processed by the MAC.
Bits 30:27: Channel/endpoint number
Bits 26:25:
00: IN/OUT token
01: Zero-length transmit packet (device IN/host OUT)
11: Channel halt command
Bit 24: Terminate (last entry for selected channel/endpoint)
Indicates the amount of free space available in the non-periodic transmit request queue.
This queue holds both IN and OUT requests.
0: Non-periodic transmit request queue is full
1: 1 location available
2: locations available
n: n locations available (0 ≤ n ≤ 8)
Others: Reserved
Indicates the amount of free space available in the non-periodic Tx FIFO.
Values are in terms of 32-bit words.
0: Non-periodic Tx FIFO is full
1: 1 word available
2: 2 words available
n: n words available (where 0 ≤ n ≤ 512)
Others: Reserved
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
detection enable
BUS
sensing comparators to detect V
BUS
detection disabled
BUS
detection enabled
BUS
USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
BUS
RM0390 Rev 4
21 20 19
VBDEN Res. Res. Res.
rw
5 4 3
Res. Res. Res. Res.
valid levels on the V
BUS
comparators are
BUS
18 17 16
PWR
Res.
DWN
rw
2 1 0
Res. Res.
PAD for USB
1137/1328
1264