Data Programming To Flash Memory - Fujitsu MB90420/5 (A) Series Hardware Manual

25.7.2 Data Programming to Flash Memory

This section explains the procedure for issuing the program command to program data to flash memory.
n Data programming to flash memory
Data can be programmed to flash memory by continuously sending the program command in the command
sequence table (see Table 25-2 of Section 25.5) to a target sector in flash memory. At completion of data
write to a target address in the fourth cycle, the automatic algorithm is executed to start programming.
• Specifying address
The only even addresses can be specified in the write data cycle. Specifying odd addresses disables
correct writing. Writing to even addresses must be performed in word data units.
Writing is possible in any address order or even beyond sector boundaries. However, execution of one
write command, permits writing of only one word.
• Precautions at data programming
Data 0 cannot be returned to data 1 by writing. When data 0 is written to data 1, the data polling algorithm
(DQ7) or toggling (DQ6) is not terminated and the flash memory is considered faulty; the timing limit
exceeding flag (DQ6) is considered as being in error, or data 1 is assumed to have been written. When
data is read in the read/reset state, the data remains 0. Only erasing enables data "0" to be set to data 1.
All commands are ignored during writing. If a hardware reset occurs during writing, data being written to
addresses are not guaranteed.
n Data programming procedure
The hardware sequence flags (see Section 25.6) can be used to check the operating state of the automatic
algorithm in flash memory. Figure 25.3 gives an example of the procedure for programming data into flash
memory. The data polling flag (DQ7) is used in this example.
Flag check data should be read from the address where data was last written.
Because the data polling flag (DQ7) and the timing limit exceeding flag (DQ5) change at the same time, the
data polling flag (DQ7) must be rechecked even if the timing limit exceeding flag (DQ5) is 1.
Similarly, because the toggle bit flag (DQ6) stops toggling at the same time the timing limit exceeding flag
(DQ5) changes to 1, toggle bit flag (DQ6) must be rechecked.
1-MBIT FLASH MEMORY
25-17