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MB90420/5 (A) SERIES F
• Software reset
A software reset generates an internal reset when "0" is written to the RST bit of the low-power
consumption mode control register (LPMCR). A software reset does not require the oscillation stabilization
wait time.
• Watchdog reset
A watchdog reset is generated by an overflow of the watchdog timer when 0 is not written to the WTE bit of
the watchdog timer control register (WDTC) within the predetermined time after the watchdog timer is
started. The oscillation stabilization wait time can be set by the clock selection register (CKSCR).
• Power-on reset
The power-on reset occurs at power-on. The oscillation stabilization wait time is fixed to 2
18
clock cycles (2
/HCLK). The reset is performed after the oscillation stabilization wait time has elapsed.
• Low-voltage detection reset
The low-voltage detection reset occurs when the power supply voltage falls lower than the predetermined
value. The oscillation stabilization wait time is fixed to 2
performed after the oscillation stabilization wait time has elapsed.
This function works only for the MB90420A/MB90425A series with the low-voltage detection reset circuit
and always starts at power-on.
• CPU Operation detection reset
The CPU operation detection reset occurs by an overflow occurs in the CPU operation detection function
counter when 0 is not written to the CL bit of the low-voltage detection reset control register (LVRC) within
the predetermined time after power-on.
This function works only for the MB90420A/MB90425A series with the CPU operation detection reset
circuit and always starts at power-on.
Remark: Definition of clocks
HCLK : Oscillation clock frequency
MCLK : Main clock frequency
SCLK : Sub-clock frequency
φ
: Machine clock (CPU operating clock) frequency
1/φ
: Machine cycle (CPU operating clock cycle)
For details, see Section 4.1.
Note:
At a reset in the stop or sub-clock modes, the oscillation stabilization wait time of 2
32.77 ms when HCLK = 4 MHz) is taken.
For details, see Section 4.1.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
3-4
18
oscillation clock cycles (2
18
oscillation
18
/HCLK). A reset is
17
/HCLK (about
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