Fujitsu MB90420/5 (A) Series Hardware Manual page 94

MB90420/5 (A) SERIES F
• System clock generation circuit
The oscillation clock (HCLK) is generated by the external oscillator. An external clock can also be input.
• Sub-clock generation circuit
The sub-clock generation circuit generates sub-clocks (SCLK) using the eternal oscillator. External clocks
can also be input.
• PLL multiplication circuit
The oscillation clock is multiplied using the PLL oscillation, and is supplied to the CPU clock selector.
• Clock selector
The clock to be supplied to the CPU clock control and resource clock circuit is selected from the main clock
and four different PLL clocks.
• Clock select register (CKSCR)
This register switches between the oscillation clock and the PLL clock, selects the oscillation stabilization
wait time and the PLL clock multiplication rate.
• Oscillation stabilization wait time selector
This circuit selects the oscillation stabilization wait time for the oscillation clock at canceling the stop mode,
or at a watchdog reset. One of the four different time-base timer outputs is selected.
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MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
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