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MB90420/5 (A) SERIES F
12.7 Operation of UART
The UART provides master/slave mode connection communication function (operation mode 1) in addition to
normal bidirectional serial communication function (operation modes 0 and 2).
n Operation of UART
• Operating mode
The UART has three types of operation modes from mode 0 to mode 2. As shown in Table 12-15, they
can be selected by the inter-CPU connection mode or data transfer mode.
Operation Mode
0
Normal mode
1
Multiprocessor mode
2
Normal mode
— : Setting prohibited
*1 : +1 is the address/data select bit (A/D) used for controlling communications.
*2 : During reception, only one bit can be detected as the stop bit.
Note:
The UART operation mode 1 is only used by the master with the master/slave mode connection.
• Inter-CPU connection mode
Either 1-to-1 connection (normal mode) or master/slave mode connection (multiprocessor mode) can be
selected. In both modes, the data length, parity, synchronous or asynchronous mode, etc., must be the
same for all CPUs. The operation modes are selected as follows.
– For the 1-to-1 connection, the same operation mode (either operation mode 0 or 2) must be used for
the two CPUs. For the asynchronous mode, select operation mode 0; for the synchronous mode select
operation mode 2.
– For the master/slave mode connection, operation mode 1 is used; select operation mode 1 and use it
as the master. For this connection, select No parity.
• Synchronous/asynchronous
For the operation modes, either the asynchronous mode (start-stop synchronization) or the clock-
synchronous mode can be selected.
• Signal mode
The UART can only handle the NRZ (Non Return to Zero) data format.
• Operation enable
The UART has operation enable bits, TXE and RXE, to control transmission and reception respectively.
When an operation in progress is disabled, the following processing is performed.
– If reception is disabled while it is in progress (when data is being input to the receive shift register),
reception of the frame is completed and then the reception is stopped after the receive data is stored in
the input data register (SIDR0/1).
– If transmission is disabled while it is in progress (when data is being output from the transmit register),
transmission is stopped after there is no data left in the output data register (SODR0/1).
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
Table 12-15 Operation Mode of UART
Data Length
No Parity
With Parity
7 bits or 8 bits
1
8 + 1*
8
12-28
Synchronous/
Asynchronous
Asynchronous
—
Asynchronous
—
Synchronous
Length of Stop Bit
2
1 bit or 2 bits*
None
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