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23.6.3 Last Event Indicate Register (LEIR)
This register indicates the last event.
The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to 1, other
bits are set to 0s.
n Last event indicate register (LEIR)
Address: 003C02
(CAN0)
H
Address: 003D02
(CAN1)
H
Read/write →
Initial value →
[bit 7] NTE: Node status transition event bit
When this bit is 1, node status transition is the last event.
This bit is set to 1 at the same time the NT bit of the control status register (CSR) is set.
This bit is also set to 1 irrespective of the setting of the node status transition interrupt enable bit (NIE) of
CSR.
Writing 0 to this bit sets the NTE bit to 0. Writing 1 to this bit is ignored.
1 is read when a read-modify-write instruction is executed.
[bit 6] TCE: Transmit completion event bit
When this bit is 1, it indicates that transmit completion is the last event.
This bit is set to 1 at the same time as any one of the bits of the transmit completion register (TCR). This
bit is also set to 1, irrespective of the settings of the bits of the transmit interrupt enable register (TIER).
Writing 0 sets this bit to 0. Writing 1 to this bit is ignored.
1 is read when a read-modify-write instruction is performed.
When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the message buffer number
completing the transmit operation.
[bit 5] RCE: Receive completion event bit
When this bit is 1, it indicates that receive completion is the last event.
This bit is set to 1 at the same time as any one of the bits of the receive complete register (RCR). This bit
is also set to 1 irrespective of the settings of the bits of the receive interrupt enable register (RIER).
Writing 0 sets this bit to 0. Writing 1 to this bit is ignored.
1 is read when a read-modify-write instruction is performed.
When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the message buffer number
completing the receive operation.
[bits 3 to 0] MBP3 to MBP0: Message buffer pointer bits
When the TCE or RCE bit is set to 1, these bits indicate the corresponding numbers of the message
buffers (0 to 15). If the NTE bit is set to 1, these bits have no meaning.
Writing 0 sets these bits to 0s. Writing 1 to these bits is ignored.
1s are read when a read-modify-write instruction is performed.
If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is not neccessarily
the same as indicated by LEIR. Other CAN events may occur in the time from interrupt request to the
LEIR access by the interrupt handler.
CAN CONTROLLER
7
6
5
NTE
TCE
RCE
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
23-15
4
3
2
—
MBP3
MBP2
(—)
(R/W)
(R/W)
(—)
(0)
(0)
← Bit No.
1
0
MBP1
MBP0
(R/W)
(R/W)
(0)
(0)
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