Sub-Second Data Register - Fujitsu MB90420/5 (A) Series Hardware Manual

18.2.2 Sub-second Data Register

The sub-second data register stores reload values for the 21-bit prescaler that divides the oscillation clock.
The reload value is usually set so that the output cycle of the 21-bit prescaler becomes precisely 1 second.
n Sub-second data register
Sub-second data register
Address: 00395C
H
Read/write
Initial value
Sub-second data register
Address: 00395B
H
Read/write
Initial value
Sub-second data register
Address: 00395A
H
Read/write
Initial value
[bits 20 to 0] D20 to D0
The sub-second data register stores reload values for the 21-bit prescaler. The reload value is reloaded
after the reload counter reaches 0. When changing all 3 bytes, be careful not to perform the reload
operation between write instructions.
combination of a new data byte and old data byte. Usually, the sub-second register should be rewritten
while the start bit is 0. When the sub-second register is set to 0, the 21-bit prescaler does not operate at
all.
The input clock frequency is designed to be always equal to 4 MHz of the oscillation clock. The reload
value for the 21-bit prescaler is typically 1E847F in hexadecimal, which is equal to "2
two such prescalers are combined, clock signals with a cycle of precisely 1 second are issued.
TIMEPIECE TIMER
bit 7 bit 6 bit 5
–– –– ––
— — —
— — —
bit 15 bit 14 bit 13
D15 D14 D13
(R/W) (R/W) (R/W)
(X) (X) (X)
bit 7 bit 6 bit 5
D7 D6 D5
(R/W) (R/W) (R/W)
(X) (X) (X)
Otherwise, the 21-bit prescaler will load wrong data with a
18-7
bit 4 bit 3 bit 2
D20 D19 D18
(R/W) (R/W) (R/W)
(X) (X) (X)
bit 12 bit 11 bit 10
D12 D11 D10
(R/W) (R/W) (R/W)
(X) (X) (X)
bit 4 bit 3 bit 2
D4 D3 D2
(R/W) (R/W) (R/W)
(X) (X) (X)
Bit No.
bit 1 bit 0
D17 D16
WTBRH
(R/W) (R/W)
(X) (X)
Bit No.
bit 9 bit 8
D9 D8
WTBRM
(R/W) (R/W)
(X) (X)
Bit No.
bit 1 bit 0
D1 D0 WTBRL
(R/W) (R/W)
(X) (X)
× 5
7 6
–1". So, when