Baud Rate By Dedicated Baud Rate Generator; Table 12-11 Selection Of Division Ratio Of Machine Clock Prescaler; Table 12-12 Selection Of Division Ratio To Obtain Synchronous Baud Rate - Fujitsu MB90420/5 (A) Series Hardware Manual

F2mc-16lx family 16-bit microcontrollers
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MB90420/5 (A) SERIES F

12.6.1 Baud Rate by Dedicated Baud Rate Generator

The baud rate that can be set when the output clock of the dedicated baud rate generator is selected as the
transfer clock of the UART is shown.
n Baud rate by dedicated baud rate generator
When generating the transfer clock by the dedicated baud rate generator, the machine clock is divided by
the machine clock prescaler and then divided by the transfer clock division ratio selected by the clock
selector. The machine clock division ratio is the common to the asynchronous and synchronous modes, but
the transfer clock division ratio selects the internally and separately set value for the asynchronous and
synchronous modes.
Consequently, the actual transfer rate is obtained by the following expression.
Asynchronous baud rate = φ × (prescaler clock division ratio) × (asynchronous transfer clock division
ratio)
Synchronous baud rate = φ × (prescaler clock division ratio) × (synchronous transfer clock division ratio)
φ: Machine clock frequency
• Division ratio of prescaler (common to asynchronous and synchronous modes)
The division ratio of the machine clock is specified by the DIV3 to DIV0 bits of the CDCR0/1 as shown in
Table 12-11.

Table 12-11 Selection of Division Ratio of Machine Clock Prescaler

• Synchronous transfer clock division ratio
The division ratio to obtain the synchronous baud rate is specified by the CS2 to CS0 bits of the mode
register (SMR) as shown in Table 12-12.

Table 12-12 Selection of Division Ratio to Obtain Synchronous Baud Rate

CS2
0
0
0
0
1
1
φ = 16 MHz (machine cycle)
div = 4
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
MD
DIV3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CS1
CS0
synchronous
0
0
0
1
1
0
1
1
0
0
0
1
DIV2
DIV1
DIV0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CLK-
Calculation
Expression
(φ ÷ div)/1
16 M
(φ ÷ div)/2
8 M
(φ ÷ div)/4
4 M
(φ ÷ div)/8
2 M
(φ ÷ div)/16
1 M
(φ ÷ div)/32
500 k
12-24
div
Stop
1
2
3
4
5
6
7
8
SCKI
(φ ÷ div)/1
(φ ÷ div)/2
(φ ÷ div)/4
(φ ÷ div)/8
(φ ÷ div)/16
(φ ÷ div)/32

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