Detailed Explanation Of Registers For Ppg Timer - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

13.3.2 Detailed Explanation of Registers for PPG Timer

The PPG timer has following four registers:
• PPG control status register (PCNT0 to PCNT2)
• PPG decrement counter register (PDCR0 to PDCR2)
• PPG cycle setting register (PCSR0 to PCSR2)
• PPG duty setting register (PDUT0 to PDUT2)
n PPG control status register (PCNT)
PPG control status register
(upper)
Address: ch0 00002B
Address: ch1 00002D
Address: ch2 00002F
PPG Control status register
(lower)
Address: ch0 00002A
Address: ch1 00002C
Address: ch2 00002E
[bit 15] CNTE: Timer enable bit
This bit enables operation of the 16-bit decrement counter.
[bit 14] STGR: Software trigger bit
When 1 is written to this bit, the software trigger is caused.
0 is always read from the STGR bit.
[bit 13] MDSE: Mode select bit
This bit selects the PWM operation that issues a pulse continuously or the one-shot operation that issues
a single pulse. It cannot be rewritten during operation.
[bit 12] RTRG: Restart enable bit
This bit enables restart by the software trigger. It cannot be rewritten during operation.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
bit 15 bit 14 bit 13
CNTE STGR MDSE RTRG CKS1 CKS0 PGMS
H
H
(R/W) (R/W) (R/W)
H
(0) (0)
bit 7 bit 6
EGS1 EGS0
H
H
(R/W) (R/W)
H
(0) (0)
0 Stops
1 Enables
0 PWM operation
1 One-shot operation
0 Disables restart
1 Enables restart
bit 12 bit 11
(R/W) (R/W)
(0) (0) (0)
bit 5 bit 4 bit 3
IREN IRQF IRS1
(R/W) (R/W) (R/W)
(0) (0) (0)
(initial value)
(initial value)
(initial value)
13-6
bit 10 bit 9 bit 8
––
(R/W) (R/W) (–)
(0) (0) (–)
bit 2 bit 1 bit 0
IRS0 POEN OSEL
(R/W) (R/W) (R/W)
(0) (0) (0)
PCNTH0 to 2
Read/write
Initial value
PCNTL0 to 2
Read/write
Initial value