Fujitsu MB90420/5 (A) Series Hardware Manual page 19

Table 1-1 Overview of MB90420/5 (A) Series.............................................................................1-3
Table 1-2 Features of MB90420/5 (A) Series..............................................................................1-4
Table 1-3 Pin Description ..........................................................................................................1-11
Table 1-4 I/O Circuits .................................................................................................................1-14
Table 2-1 Access Space for Each Bank Register and Major Use of Access Space ..............2-9
Table 2-2 Addressing and Default Spaces ..............................................................................2-10
Table 2-3 Initial Values of Dedicated Registers ......................................................................2-15
Table 2-4 Stack Address Specification ....................................................................................2-19
Table 2-5 Interrupt Level Mask Register (ILM) and Interrupt Level (high/low).....................2-24
Table 2-6 Typical Function of the General-Purpose Register ...............................................2-29
Table 2-7 Bank Select Prefix .....................................................................................................2-31
Table 2-8 Instructions Unaffected by Bank Select Prefix ......................................................2-31
Table 2-9 Instructions Requiring Care When Using Bank Select Prefix ..............................2-32
Table 2-10 Instructions Requiring Care When Using Bank Select Prefix (CMR)...................2-32
Table 2-11 Instructions Requiring Care When Using Flag Change Inhibit Prefix (NCC) ......2-33
Table 2-12 Prefix Code and Interrupt/hold Inhibit Instruction .................................................2-34
Table 3-1 Reset Factor.................................................................................................................3-3
Table 3-2 Reset Factors and Oscillation Stabilization Wait Times .........................................3-5
Table 3-3 Oscillation Stabilization Wait Time Based on Setting of
Clock Selection Register (CKSCR) ............................................................................3-6
Table 3-4 Correspondence of Reset Factor Bit Value and Reset Factor..............................3-11
Table 4-1 Function of Each Bit of Clock Select Register (CKSCR).........................................4-8
Table 5-1
Function of Each Bit of Low -pow er Consum ption M ode Control Register (LPM CR)..5-8
Table 5-2 Instructions At Transition To Low-power Consumption Mode ..............................5-9
Table 5-3 Operating State in Standby Mode............................................................................5-11
Table 5-4 Operation State in Low-power Consumption Mode...............................................5-20
Table 5-5 Each Pin State in Single Chip Mode ........................................................................5-21
Table 6-1 Interrupt Vectors..........................................................................................................6-5
Table 6-2 Interrupt Source, Interrupt Vector, and Interrupt Control Register........................6-6
Table 6-3 Interrupt Control Register List ...................................................................................6-7
Table 6-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels.............6-11
Table 6-5 Correspondence between EI2OS Channel Select Bits and Descriptor Addresses6-12
Table 6-6 Relationships between EI2OS Status Bits and EI2OS Status...............................6-12
Table 6-7 Mechanism Related to Hardware Interrupt .............................................................6-13
Table 6-8 Hardware Interrupt Inhibit Instructions...................................................................6-14
Table 6-9 compensation Value (Z) of Interrupt Handling Time..............................................6-20
Table 6-10 Correspondence between Channel Number and Descriptor Address ................6-25
Table 6-11 EI2OS Executing Time ..............................................................................................6-31
Table 6-12 Compensation Value for Data Transfer at EI2OS Executing Time .......................6-31
Table 6-13 Compensation Value (Z) for Interrupt Handling Time............................................6-32
Table 7-1 Setting of Mode Pins ...................................................................................................7-4
Table 7-2 Bus Mode Setting Bits and Functions.......................................................................7-5
Table 7-3 Relationships between Mode Pins and Mode Data..................................................7-6
Tables
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