Fujitsu MB90420/5 (A) Series Hardware Manual page 18

Fig. 20.1 Block Diagram of Sound Generator ........................................................................... 20-3
Fig. 20.2 Relationship between Tone Signal and Register Value ........................................... 20-7
Fig. 20.3 Relationship between Register Value and PWM Pulse ............................................ 20-8
Fig. 21.1 Block Diagram of ROM Correction ............................................................................. 21-3
Fig. 21.2 System Structure Example ......................................................................................... 21-6
Fig. 21.3 ROM Correction Processing Flow .............................................................................. 21-7
Fig. 21.4 ROM Correction Processing Flow .............................................................................. 21-8
Fig. 21.5 ROM Correction Processing Flow Diagram............................................................... 21-9
Fig. 22.1 Block Diagram of ROM Mirror Function Select Module ........................................... 22-3
Fig. 22.2 Memory Area................................................................................................................. 22-4
Fig. 23.1 Block Diagram of CAN Controller............................................................................... 23-4
Fig. 23.2 Node Status Transition Diagram............................................................................... 23-13
Fig. 23.3 Bit Time Segment in CAN Specification................................................................... 23-17
Fig. 23.4 Bit Time Segment in CAN Controller........................................................................ 23-17
Fig. 23.5 Transmission Flowchart of the CAN Controller ...................................................... 23-33
Fig. 23.6 Flowchart Determining Message Buffer (x) where Receive Messages Stored .... 23-35
Fig. 23.7 Reception Flowchart for the CAN Controller........................................................... 23-36
Fig. 23.8 Example of Receive Interrupt Processing ............................................................... 23-40
Fig. 23.9 Examples of Operation of Multi-level Message Buffer ........................................... 23-42
Fig. 24.1 Block Diagram of Detection Reset Circuit for Low Voltage and CPU Operation... 24-4
Fig. 24.2 Low Voltage and CPU Operation Detection Reset Control Register (LVRC) ......... 24-5
Fig. 25.1 Block Diagram for Entire Flash Memory .................................................................... 25-4
Fig. 25.2 Sector Configuration of 1-Mbit Flash Memory .......................................................... 25-5
Fig. 25.3 Example of Data Programming Procedure .............................................................. 25-18
Fig. 25.4 Example of Sector Erasing Procedure ..................................................................... 25-20
Fig. 26.1 Example of Serial Write Connection for MB90F428/A
(User Power Supply Used)........................................................................................... 26-5
Fig. 26.2 Example of Serial Write Connection for MB90F428/A
(Power Supplied from the Writer) ............................................................................... 26-7
Fig. 26.3 Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used)........................................................................................... 26-9
Fig. 26.4 Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied from the Writer) ............................................................................. 26-11
xviii