Overview Of Rom Correction; Fig. 21.1 Block Diagram Of Rom Correction - Fujitsu MB90420/5 (A) Series Hardware Manual

This chapter explains the functions and operations of ROM correction.

21.1 Overview of ROM Correction

When the setting of the address is the same as the ROM correction address registers, the INT9 instruction
will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be
achieved.
There are two address registers, in each containing a compare enable bit. When the address register and
the program counter match, and when the compare enable bit is at '1', then the CPU will be forced to
execute INT9 instruction.
n Block diagram of ROM correction
Figure 21.1 shows a block diagram of the ROM correction.
Address latch
ROM correction address
Enable bit
Detection bit
Reset
2
F MC-16LX bus
n ROM correction register
PADR0 address: 1FF2
PADR1 address: 1FF5
Bit No.
PACSR Address: 00009E
ROM CORRECTION
register
Set

Fig. 21.1 Block Diagram of ROM Correction

byte
/1FF1 /1FF0
H H H
/1FF4 /1FF3
H H H
7 6
Reserved Reserved
H
— —
byte byte
5 4 3
AD1E
Reserved Reserved
— — R/W
21-3
2
F MC-16LX
CPU core
Access Initial value
R/W undefined
R/W undefined
2 1 0
AD0E
Reserved Reserved
— R/W —
Initial value
----0-0-
B