Fujitsu MB90420/5 (A) Series Hardware Manual page 21

Table 9-6 Time-base Timer Counter Clear and Oscillation Stabilization Wait Time............9-15
Table 10-1 Operation Mode of 16-bit Reload Timer ..................................................................10-3
Table 10-2 Interval Time of 16-bit Reload Timer .......................................................................10-4
Table 10-3 16-bit Reload Timer Interrupt and EI2OS ................................................................10-4
Table 10-4 Pins of 16-bit Reload Timer ......................................................................................10-7
Table 10-5 Function of Each Bit of Timer Control Status Register (upper)
(TMCSR0, TMCSR1: H)...........................................................................................10-10
Table 10-6 Function of Each Bit of Timer Control Status Register (lower) (TMCSR0/1L) ..10-12
Table 10-7 Interrupt Control Bits and Interrupt Factors of 16-bit Reload Timer..................10-15
Table 10-8 16-bit Reload Timer Interrupt and EI2OS ..............................................................10-15
Table 12-1 Function of UART ......................................................................................................12-3
Table 12-2 Operation Mode of UART..........................................................................................12-4
Table 12-3 Interrupt Related to UART and EI
Table 12-4 UART Pins ..................................................................................................................12-8
Table 12-5 Function of Each Bit of Control Register (SCR0/1)..............................................12-11
Table 12-6 Function of Each Bit of Mode Register (SMR0/1).................................................12-13
Table 12-7 Function of Each Bit of Status Register (SSR0/1)................................................12-15
Table 12-8 Communication Prescaler ......................................................................................12-17
Table 12-9 UART Interrupt Control Bit and Interrupt Factor..................................................12-18
Table 12-10 Interrupt of UART and EI
Table 12-11 Selection of Division Ratio of Machine Clock Prescaler .....................................12-24
Table 12-12 Selection of Division Ratio to Obtain Synchronous Baud Rate .........................12-24
Table 12-13 Selection of Division Ratio to Obtain Asynchronous Baud Rate.......................12-25
Table 12-14 Baud Rate and Reload Value..................................................................................12-26
Table 12-15 Operation Mode of UART........................................................................................12-28
Table 12-16 Selection of Master/Slave Mode Communication Function ................................12-36
Table 14-1 Combination of Bias and Duty .................................................................................14-3
Table 14-2 LCD Driving Voltage Setting ....................................................................................14-8
Table 14-3 Function of Each Bit of LCDC Control Register Lower (LCRL) ..........................14-14
Table 14-4 Function of Each Bit of LCDC Control Register Higher (LCRH).........................14-15
Table 14-5 Relationship between Common/Segment Output Pins and Display RAM,
and Pins also Serving as General-purpose Ports................................................14-17
Table 14-6 Relationship between Duty, Common Output Pins, and Display RAM Bits......14-17
Table 14-7 Example of Display RAM Data ...............................................................................14-19
Table 14-8 Example of Display RAM Data ...............................................................................14-22
Table 14-8 Example of Display RAM Data ...............................................................................14-25
Table 15-1 Selection of M otor Drive Signals and Settings of PW M Select Registers 1 and 2 ....15-9
Table 16-1 Overview of DTP/External Interrupt.........................................................................16-3
Table 16-2 DTP/External Interrupt Circuit and EI
Table 16-3 Pins of DTP/External Interrupt Circuit.....................................................................16-7
Table 16-4 Function of Each Bit of DTP/Interrupt Factor Register (EIRR) .............................16-8
Table 16-5 Function of Each Bit of DTP/Interrupt Enable Register (ENIR) ............................16-9
Table 16-6 Correspondence between DTP/Interrupt Control Registers (EIRR and ENIR)
and Each Channel .....................................................................................................16-9
2
OS......................................................................12-4
2
OS ..................................................................................12-19
2
OS ...............................................................16-4
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