Table 8-10 State Of Port 1 Pins - Fujitsu MB90420/5 (A) Series Hardware Manual

• Operation in stop mode or time-base timer mode
When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is
1, at a transition to the stop mode or time-base timer mode, the pin is set to the high-impedance state.
Because the output buffer is set forcibly to OFF irrespective of the value of the DDR1 register. Input is
fixed to prevent leakage due to opening of input. Table 8-10 shows the state of the port 1 pins.
Pin Name
P10/PPG2 to
P15/IN0
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
I/O PORT

Table 8-10 State of Port 1 Pins

Normal
Sleep Mode
Operation
General- General-
purpose I/O purpose I/O
port pin port pin
Stop Mode or
Time-base Timer
Mode (SPL = 0)
General-purpose
I/O port pin
8-15
Stop Mode or Time-
base Timer Mode
(SPL = 1)
Input cut off, and
output becomes Hi-Z