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MB90420/5 (A) SERIES F
Table 10-6 Function of Each Bit of Timer Control Status Register (lower) (TMCSR0/1L)
Bit Name
bit 6
OUTE:
Timer output enable bit
bit 5
OUTL:
Pin output level select bit
bit 4
RELD:
Reload select bit
INTE:
bit 3
Interrupt request enable
bit
bit 2
UF:
Underflow interrupt
request flag bit
bit 1
CNTE:
Count enable bit
bit 0
TRG:
Software trigger bit
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
• This bit enables and disables output of the timer output pin.
• When this bit is 0, the pin becomes a general-purpose port pin; when this bit is
1, the pin becomes a timer output pin.
• In the reload mode, the output wave of the timer output pin is a toggle wave; in
the one-shot mode, the output wave of the timer output pin is a rectangular
wave indicating that counting is in progress.
• This bit selects the output level of the timer output pin.
• The pin level output when this bit is 0 is opposite to the output when this bit is
1.
• This bit enables the reload operation.
• When this bit is 1, the reload mode is enabled to load the value of the reload
register into the counter concurrently with the underflow to continue counting.
• When this bit is 0, the one-shot mode is enabled and an underflow stops
counting.
• This bit enables and disables the interrupt request output to the CPU.
• When this bit and the interrupt request flag bit (UF) are 1, an interrupt request
is output.
• This bit is set to 1 when a counter underflow occurs.
• When 0 is written to this bit, it is cleared; when 1 is written to this bit, the
operation is not affected.
• This bit is also cleared when the EI
• This bit enables and disables counting.
• When 1 is written to this bit, the trigger wait state occurs.
When the start trigger occurs, the actual counting is started.
• This bit starts the interval timer function or the counter function by software.
• When 1 is written to this bit, software is triggered to load the value of the
reload register into the counter to start counting. Writing 0 to this bit has no
meaning.
• When CNTE = 1, the trigger input using this bit is always enabled irrespective
of the operation mode.
10-12
Function
2
OS occurs.
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