Fujitsu MB90420/5 (A) Series Hardware Manual page 163

n Program example for EI
2
(1) The EI OS is started by detecting the H level of the signal input to the INT0 pin.
(2) When the H level is input to the INT0 pin, EI
memory address 3000
(3) The transfer data byte count is 100. After 100 bytes are transferred, an interrupt is generated by
termination of the EI
• Coding example
DDR1 EQU
ENIR EQU
EIRR EQU
ELVR EQU
ICR00 EQU
BAPL EQU
BAPM EQU
BAPH EQU
ISCS EQU
IOAL EQU
IOAH EQU
DCTL EQU
DCTH EQU
ERO EQU
STACK SSEG
RW
STACK_T RW
STACK ENDS
; - - - - - Main program - - - - - - - - - - - - - - - - - - - - - - - - -
CODE CSEG
START:
AND
MOV
MOV
MOV
MOVW
MOVW
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
OR
:
LOOP: BRA
2
OS program
.
H
2
OS transfer.
; Port 1 direction register
000011
H
; Interrupt/DTP enable register
000030
H
; Interrupt/DTP factor register
000031
H
; Request level setting register
000032
H
; Interrupt control register 00
0000B0
H
; Lower of buffer address pointer
000100
H
; Middle of buffer address pointer
000101
H
; Upper of buffer address pointer
000102
H
; EI2OS status
000103
H
; Lower of I/O address pointer
000104
H
; Upper of I/O address pointer
000105
H
; Lower of data counter
000106
H
; Upper of data counter
000107
H
; External interrupt request flag bit defined
EIRR:0
; Stack
100
1
; I flag of CCR in PS cleared to disable interrupt
CCR,#0BF
H
; Register bank pointer set
RP,#00
; System stack set
A,#!STACK_T
SSB,A
; Stack pointer set
A,#STACK_T
; In this case, S flag = 1, so SSP set
SP,A
; Set P10/INT0 pin to input
I:DDR1,#00000000
B
; Buffer address set (003000
BAPL,#00
H
BAPM,#30
H
BAPH,#00
H
; I/O Address not updated, byte transfer performed, and buffer address
ISCS,#00010001
B
; Data transferred from I/O to buffer, and termination by resource
; Transfer destination address set (port 0: 000000
IOAL,#00
H
IOAH,#00
H
; Transfer byte count set (100 bytes)
DCTL,#64
H
DCTH,#00
H
I:ICR00,#00001000
B
; Set INT0 as an H-level request
I:ELVR,#00000001
B
; INT0 interrupt factor cleared
I:EIRR,#00
H
; INT0 interrupt enabled
I:ENIR,#01
H
; ILM in PS set to level 7
ILM,#07
H
; I flag of CCR in PS set to enable the interrupt
CCR,#40
H
; Infinite loop
LOOP
INTERRUPT
2
OS is started and the data of port 0 is transferred to
updated
; EI2OS channel = 0, EI2OS enabled, and interrupt level 0 (highest)
6-37
)
H
)
H