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8.7.2 Operation of Port 5
The operation of port 5 is explained.
n Operation of port 5
• Operation at output port
– When the bit of the corresponding DDR5 register is set to 1, the pin becomes an output port pin.
– When data is written to the PDR5 register at the output port, data is held at the output latch in PDR and
then output to that output port pin as it is.
– When the PDR5 register is read, the value of the pin (same value as output latch in PDR) is read.
Note:
When a read-modify-write family instruction (such as bit set instruction) is used for the port data
register, the target bit becomes the specified value and the bits set to output in the DDR register are
unaffected. However, the bits set to input in the DDR register are affected. The input values of the
corresponding pins are written to the output latch and then output to the pins. Consequently, when
switching a bit that is used as input to output, write the output data to the PDR register, and then set
the DDR register to output.
• Operation at input port
– When the bit of the corresponding DDR5 register is set to 0, the pin becomes an input port pin.
– When the pin is an input port pin, the output buffer is set to OFF and the pin is set to the high-
impedance state.
– When data is written to the PDR5 register, data is held at the output latch in PDR, but not output to the
pin.
– When the PDR5 register is read, the level value (0 or 1) of the pin is read.
• Operation when pin used as resource output pin
When using a pin as a resource output pin, set the output enable bit for the resource. At I/O switching, the
output enable bit for a resource is preferred to other bits, so a pin becomes a resource output pin when the
output enable bit for each resource is enabled even if the bit of the DDR5 register is 0. Even when the
output for a resource is enabled, the value of the pin can be read, so the output value of a resource can be
read.
• Operation when pin used as resource input pin
For a port that also serves as a resource input pin, a pin value is always input to the resource input pin.
When using external signals for a resource input pin, write 0 to the DDR5 register to set the pin as an input
port.
• Operation at reset
– When the CPU is reset, the value of the DDR5 register is initialized to 0. Consequently, all output
buffers are set to OFF (the pin becomes an input port pin), making the pin to be set to the high-
impedance state.
– The PDR5 register is not initialized by a reset. So, when using a pin as an output port, it is necessary to
set output data in the PDR5 register and then set the DDR5 register that corresponds to that register to
output.
I/O PORT
8-29
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