Fig. 10.10 State Transition Diagram Of Counter - Fujitsu MB90420/5 (A) Series Hardware Manual

n Operation state of counter
The counter state is determined by the CNTE bit of the timer control status register (TMCSR0/1L,
TMCSR0/1H) and the wait signal of internal signal. The state that can be set includes the stop state (stop
state), start trigger wait state (wait state), and operating state (run state). The state transition diagram of the
counter is shown in Figure 10.10.
Reset
CNTE = 0
WAIT state
TIN pin: only trigger input enabled
TOT pin: initial value output
Counter:
value at stop state retained,
undefined from immediately
after a reset to loading
(software trigger)
External trigger from TIN
WAIT : Wait signal (internal signal)
TRG : Software trigger bit of the timer control status register (TMCSR)
CNTE : Count enable bit of the timer control status register (TMCSR)
UF : Underflow interrupt request flag bit of the timer control status register (TMCSR)
RELD : Reload select bit of the timer control status register (TMCSR)
16-BIT RELOAD TIMER
STOP state
TIN pin: input disabled
TOT pin: general-purpose port
Counter: value at stop state held,
CNTE = 1/TRG = 0
CNTE = 1, WAIT = 1
TRG = 1
LOAD
Loading value of reload register to
counter
: State transition by hardware
: State transition by register access

Fig. 10.10 State Transition Diagram of Counter

CNTE = 0, WAIT = 1
undefined immediately
after a reset
CNTE = 1/TRG = 1
UF=1 &
RELD = 0
(One-shot
mode)
UF = 1 &
RELD = 1
(Reload mode)
CNTE = 1, WAIT = 0
10-17
CNTE = 0
CNTE = 1, WAIT = 0
RUN state
TIN pin: functions as TIN pin
TOT pin: functions as TOT pin
Counter: running
TRG = 1
(software trigger)
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