Fujitsu MB90420/5 (A) Series Hardware Manual page 16

Fig. 11.1 Block Diagram .............................................................................................................. 11-4
Fig. 11.2 Capture Timing Example for Input Capture ............................................................ 11-14
Fig. 11.3 Capture Timing for Input Signal ............................................................................... 11-14
Fig. 11.4 Clearing Counter by Overflow................................................................................... 11-15
Fig. 11.5 Clearing Counter when Value of 16-bit Free-run Timer Matches
Value of Compare Clear Register ............................................................................. 11-15
Fig. 11.6 Clearing Timing of 16-bit Free-run Timer................................................................. 11-16
Fig. 11.7 Count Timing of 16-bit Free-run Timer..................................................................... 11-16
Fig. 12.1 Block Diagram of UART ............................................................................................... 12-6
Fig. 12.2 Block Diagram of Pins of UART .................................................................................. 12-8
Fig. 12.3 List of UART Registers ................................................................................................ 12-9
Fig. 12.4 Control Register (SCR0/1) ......................................................................................... 12-10
Fig. 12.5 Mode Register (SMR0/1) ............................................................................................ 12-12
Fig. 12.6 Status Register (SSR0/1) ........................................................................................... 12-14
Fig. 12.7 Input Data Register (SIDR0/1) ................................................................................... 12-16
Fig. 12.8 Output Data Register (SODR0/1)............................................................................... 12-16
Fig. 12.9 Reception and Timing of Flag Set ............................................................................ 12-20
Fig. 12.10 Transmission and Timing of Flag Set ...................................................................... 12-21
Fig. 12.11 UART Baud Rate Selector.......................................................................................... 12-23
Fig. 12.12 Baud Rate Selector by Internal Timer (16-bit Reload Timer) ................................. 12-26
Fig. 12.13 Baud Rate Selector by External Clock ..................................................................... 12-27
Fig. 12.14 Format of Transfer Data (operation mode 0 or 1) ................................................... 12-29
Fig. 12.15 Transmit Data when Parity Enabled ......................................................................... 12-30
Fig. 12.16 Format of Transfer Data (operation mode 2) ........................................................... 12-31
Fig. 12.17 Setting of Operation Mode 0 for UART1................................................................... 12-33
Fig. 12.18 Example of Bidirectional Communication Connection for UART1 ....................... 12-33
Fig. 12.19 Example of Bidirectional Communication Flow ...................................................... 12-34
Fig. 12.20 Setting of Operation Mode 1 for UART1................................................................... 12-35
Fig. 12.21 Example of Master/Slave Mode Communication Connection for UART............... 12-35
Fig. 12.22 Flowchart of Master/Slave Mode Communications ................................................ 12-37
Fig. 13.1 Block Diagram of PPG Timer ...................................................................................... 13-4
Fig. 13.2 Timing of Disabling PWM Operation Restart .......................................................... 13-10
Fig. 13.3 Timing of Enabling PWM Operation Restart ........................................................... 13-10
Fig. 13.4 Timing of Disabling One-shot Operation Restart.................................................... 13-11
Fig. 13.5 Timing of Enabling One-shot Operation Restart..................................................... 13-11
Fig. 13.6 Interrupt Output Factors and Timing........................................................................ 13-12
Fig. 14.1 Block Diagram for LCD Controller/Driver .................................................................. 14-4
Fig. 14.2 Equivalent Circuit for Internal Split Resistors........................................................... 14-6
Fig. 14.3 State when Internal Split Resistors Used ................................................................. 14-7
Fig. 14.4 Brightness Adjustment when Internal Split Resistors Used ................................... 14-7
Fig. 14.5 External Split Resistor Connection Example ............................................................ 14-8
Fig. 14.6 State when External Split Resistors Used ................................................................. 14-9
Fig. 14.7 Block Diagram of Pins Related to LCD Controller/Driver ...................................... 14-11
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