Transmission Complete Register (Tcr); Transmission Interrupt Enable Register (Tier) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

23.6.12 Transmission Complete Register (TCR)

At completion of transmission by the message buffer (x), the corresponding TCx becomes 1.
If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs.
n Transmission complete register (TCR)
Address: 000047 (CAN0)
H
Address: 000077 (CAN1)
H
Read/write →
Initial value →
Address: 000046 (CAN0)
H
Address: 000076 (CAN1)
H
Read/write →
Initial value →
n Conditions for TCx = 0
• Write 0 to TCx.
• Write 1 to TREQx of the transmission request register (TREQR).
After the completion of transmission, write 0 to TCx to set it to 0. Writing 1 to TCx is ignored.
1 is read when a read-modify-write instruction is performed.
Note: If setting to 1 by completion of the transmit operation and clearing to 0 by writing occur at the same
time, the bit is set to 1.

23.6.13 Transmission Interrupt Enable Register (TIER)

This register enables or disables the transmission interrupt by the message buffer (x). The transmission
interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is
1).
n Transmission interrupt enable register (TIER)
Address: 003C0F (CAN0)
H
Address: 003D0F (CAN1)
H
Read/write →
Initial value →
Address: 003C0E (CAN0)
H
Address: 003D0E (CAN1)
H
Read/write →
Initial value →
0: Transmission interrupt disabled
1: Transmission interrupt enabled
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
15 14 13
TC15 TC14 TC13
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
TC7 TC6 TC5
(R/W) (R/W) (R/W)
(0) (0) (0)
15 14 13
TIE15 TIE14 TIE13
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
TIE7 TIE6 TIE5
(R/W) (R/W) (R/W)
(0) (0) (0)
23-22
12 11 10
TC12 TC11 TC10
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
TC4 TC3 TC2
(R/W) (R/W) (R/W)
(0) (0) (0)
12 11 10
TIE12 TIE11 TIE10
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
TIE4 TIE3 TIE2
(R/W) (R/W) (R/W)
(0) (0) (0)
← Bit No.
9 8
TC9 TC8
(R/W) (R/W)
(0) (0)
← Bit No.
1 0
TC1 TC0
(R/W) (R/W)
(0) (0)
← Bit No.
9 8
TIE9 TIE8
(R/W) (R/W)
(0) (0)
← Bit No.
1 0
TIE1 TIE0
(R/W) (R/W)
(0) (0)