Table 12-13 Selection Of Division Ratio To Obtain Asynchronous Baud Rate - Fujitsu MB90420/5 (A) Series Hardware Manual

• Asynchronous transfer clock division ratio
The clock division ratio to obtain the asynchronous baud rate is specified by the CS2 to CS0 bits of the
mode register (SMR0/1) as shown in Table 12-13.

Table 12-13 Selection of Division Ratio to Obtain Asynchronous Baud Rate

CS2 CS1
0 0
0 0
0 1
0 1
1 0
1 0
φ = 16 MHz (machine cycle)
div = 1
• Internal timer
When the internal timer is selected, setting CS2 to CS0 to 110, the baud rate is obtained using the
following expressions (when using the reload timer).
Asynchronous (start-stop synchronization) (φ ÷ N)/(16 × 2 × (n + 1))
CLK synchronous
N: count clock source of timer
n: timer reload value of timer
Note: In mode 2 (CLK synchronous mode), SCK0 is delayed for three clocks maximum against SCK1.
Theoretically, the transfer rate that can be implemented is 1/3 of the system clock frequency. In the
actual specification, it is recommended that the transfer rate is 1/4 of the system clock frequency.
• External clock
When the external clock is selected, setting CS2 to CS0 to 111, the baud rate is obtained as follows (f:
frequency of external clock).
Asynchronous (start-stop synchronization)
CLK synchronous
The maximum value of f is 1/2 of the machine clock, and the maximum value of f' is 1/8 of the machine
clock.
Asynchronous
CS0 (start - stop
synchronization)
0 76923
1 38461
0 19230
1 9615
0 500 k
1 250 k
f'
UART
Calculation Expression
(φ ÷ div)/(8 × 13 × 2)
(φ ÷ div)/(8 × 13 × 4)
(φ ÷ div)/(8 × 13 × 8)
(φ ÷ div)/(8 × 13 × 16)
(φ ÷ div)/(8 × 2 × 2)
(φ ÷ div)/(8 × 2 × 4)
(φ ÷ N)/(2 × (n + 1))
f/16
12-25
SCKI
(φ ÷ div)/(13 × 1)
(φ ÷ div)/(13 × 2)
(φ ÷ div)/(13 × 4)
(φ ÷ div)/(13 × 8)
(φ ÷ div)/2
(φ ÷ div)/4