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23.13 Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID's of messages are received, in other
words, if there is insufficient time for processing messages, more than one message buffer can be combined
into a multi-level message buffer to provide allowance for processing time of the receive message by CPU.
n Setting configuration of multi-level message buffer
To provide a multi-level message buffer, the same acceptance filter must be set in the combined message
buffers.
If the bits of the acceptance mask select register (AMSR) are set to all bits compare ((AMSx.1, AMSx.0) = (0,
0)), multi-level message configuration of message buffers is not allowed. This is because all bits compare
causes received messages to be stored irrespective of the value of the RCx bit of the receive completion
register (RCR), so receive messages are always stored in lower-numbered (lower-priority) message buffers
even if all bits compare and identical acceptance code (ID register (IDRx)) are specified for more than one
message buffer. Therefore, all bits compare and identical acceptance code should not be specified for more
than one message buffer.
Figure 23.9 shows operational examples of multi-level message buffers.
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