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10.2 Configuration of 16-bit Reload Timer
The 16-bit reload timer is composed of the following seven blocks:
• Count clock generation circuit
• Reload controller
• Output controller
• Operation controller
• 16-bit timer register (TMR0/1L, TMR0/1H)
• 16-bit reload register (TMRL0/1L, TMRLR0/1H)
• Timer control status register (TMCSR0/1L, TMCSR0/1H)
n Block diagram of 16-bit reload timer
Figure 10.1 shows the block diagram of the 16-bit reload timer.
<TMRLR1>
TMR0
<TMR1>
16-bit timer register (decrement counter) UF
Count clock generation circuit
Machine
clock φ
Pin
*1
P12/TIN0
<P07/TIN1>
Function selection
—
—
Timer control status register (TMCSR0)
*1: Channel 0 and channel 1 provided; the description in < > is for channel 1.
*2: Interrupt number
16-BIT RELOAD TIMER
Internal data bus
*1
TMRLR0
16-bit reload register
*1
CLK
3 Gate input
Prescaler
Clear
Internal clock
Input
controller
External clock
3
Select signal
—
—
—
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
<TMCSR1>
Fig. 10.1 Block Diagram of 16-bit Reload Timer
Reload signal
Wait signal
Valid clock
determination
circuit
CLK
Output signal
generator
Clock selector
Inversion
Output signal
2
*1
10-5
Reload
controller
To UART0, 1
<To A/D
converter>
generation
circuit
EN
P11/TOT0
<P06/TOT1>
Operation
controller
UF CNTE TRG
Pin
*1
Interrupt
request signal
*2
#17 (11
)
H
<#28 (1C
)>
H
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