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MB90420/5 (A) SERIES F
n Interrupt factor, interrupt vector, and interrupt control register
Table 6-2 shows the relationships between the interrupt factor except software interrupt, and interrupt vector
and interrupt control register.
Table 6-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register
Interrupt Factor
Reset
INT9 instruction
Exception handling
CAN0 RX
CAN0 TX/NS
CAN1 RX
CAN1 TX/NS
Input capture 0
DTP/external interrupt; at channel 0 detection
Reload timer 0
DTP/external interrupt; at channel 1 detection
Input capture 1
DTP/external interrupt; at channel 2 detection
Input capture 2
DTP/external interrupt; at channel 3 detection
Input capture 3
DTP/external interrupt; at channel 4/5
detection
PPG timer 0
DTP/external interrupt; at channel 6/7
detection
PPG timer 1
Reload timer 1
PPG timer 2
Watch timer (main clock)
Free-run timer over flow
End of conversion by A/D converter
Clear of free-run timer
Sound generator
Time-base timer
Clock timer (sub-clock)
Receiving by UART1
Transmitting by UART1
Receiving by UART0
Transmitting by UART0
Flash memory status
Delayed interrupt generation module
¡ : Interrupt factor can be used
× : Interrupt factor cannot be used
¥ : Interrupt factor can be used and has EI
∆ : Interrupt factor can be used when not using interrupt sources sharing ICR register
*1 : The interrupt level for resources sharing an ICR register become the same.
When two resources share an ICR register, only one can use the EI
When two resources share an ICR register and one specifies the EI
interrupt.
*2 : The priority when plural interrupts with same level are generated simultaneously
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
2
EI
OS-
Corresponded
×
#08
×
#09
×
#10
×
#11
×
#12
×
#13
×
#14
∆
#15
∆
#16
∆
#17
∆
#18
∆
#19
∆
#20
∆
#21
∆
#22
∆
#23
∆
#24
∆
#25
∆
#26
∆
#27
∆
#28
¡
#29
×
#30
×
#31
¡
#32
×
#33
×
#34
×
#35
×
#34
¥
#37
∆
#38
¥
#39
∆
#40
×
#41
×
#42
2
OS stop function
6-6
Interrupt Vector
Interrupt Control Register
No.
Address
ICR
08
FFFFDC
H
H
09
FFFFD8
H
H
0A
FFFFD4
H
H
0B
FFFFD0
H
H
ICR00
0C
FFFFCC
H
H
0D
FFFFC8
H
H
ICR01
0E
FFFFC4
H
H
0F
FFFFC0
H
H
ICR02
10
FFFFBC
H
H
11
FFFFB8
H
H
ICR03
12
FFFFB4
H
H
13
FFFFB0
H
H
ICR04
14
FFFFAC
H
H
15
FFFFA8
H
H
ICR05
16
FFFFA4
H
H
17
FFFFA0
H
H
ICR06
18
FFFF9C
H
H
19
FFFF98
H
H
ICR07
1A
FFFF94
H
H
1B
FFFF90
H
H
ICR08
1C
FFFF8C
H
H
1D
FFFF88
H
H
ICR09
1E
FFFF84
H
H
1F
FFFF80
H
H
ICR10
20
FFFF7C
H
H
21
FFFF78
H
H
ICR11
22
FFFF74
H
H
23
FFFF70
H
H
ICR12
24
FFFF6C
H
H
25
FFFF68
H
H
ICR13
26
FFFF64
H
H
27
FFFF60
H
H
ICR14
28
FFFF5C
H
H
29
FFFF58
H
H
ICR15
2A
FFFF54
H
H
2
OS.
2
OS, the remaining resource cannot use the
Priority *
Address
–
–
–
–
Higher
–
–
1
0000B0
*
H
1
0000B1
*
H
1
0000B2
*
H
1
0000B3
*
H
1
0000B4
*
H
1
0000B5
*
H
1
0000B6
*
H
1
0000B7
*
H
1
0000B8
*
H
1
0000B9
*
H
1
0000BA
*
H
1
0000BB
*
H
1
0000BC
*
H
1
0000BD
*
H
1
0000BE
*
H
Lower
1
0000BF
*
H
2
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