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MB90420/5 (A) SERIES F
23.6.1 Control Status Register (CSR)
Control status register (CSR) is prohibited from executing any bit manipulation instructions (read-modify-
write instructions).
n Control status register (CSR)
Address: 003C01
(CAN0)
H
Address: 003D01
(CAN1)
H
Read/write →
Initial value →
Address: 003C00
(CAN0)
H
Address: 003D00
(CAN1)
H
Read/write →
Initial value →
[bit 15] TS: Transmit status bit
This bit indicates whether a message is being transmitted.
0: Message not being transmitted
1: Message being transmitted
This bit is 0 even while error and overload frames are transmitted.
[bit 14] RS: Receive status bit
This bit indicates whether a message is being received.
0: Message not being received
1: Message being received
While a message is on the bus, this bit becomes 1. Therefore, this bit is also 1 while a message is being
transmitted. This bit does not necessarily indicates whether a receive message passes through the
acceptance filter.
As a result, when this bit is 0, it implies that the bus operation is stopped (HALT = 0); the bus is in the
intermission/bus idle or a error/overload frame is on the bus.
[bit 10] NT: Node status transition flag
If the node status is changed to increment, or from bus off to error active, this bit is set to 1.
In other words, the NT bit is set to 1 if the node status is changed from error active (00) to warning (01),
from warning (01) to error passive (10), from error passive (10) to bus off (11), and from bus off (11) to
error active (00). Numbers in parentheses indicate the values of NS1 and NS0 bits.
When the node status transition interrupt enable bit (NIE) is 1, an interrupt is generated. Writing 0 sets
the NT bit to 0. Writing 1 to the NT bit is ignored. 1 is read when a Read-modify-write instruction is
performed.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
15
14
13
TS
RS
—
(R)
(R)
(—)
(0)
(0)
(—)
7
6
5
TOE
—
—
(R/W)
(—)
(—)
(0)
(—)
(—)
23-12
12
11
10
—
—
NT
(—)
(—)
(R/W)
(—)
(—)
(0)
4
3
2
—
—
NIE
(—)
(—)
(R/W)
(—)
(—)
(0)
← Bit No.
9
8
NS1
NS0
(R)
(R)
(0)
(0)
← Bit No.
1
0
—
HALT
(—)
(R/W)
(—)
(1)
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