Data Register X (X = 0 To 15) (Dtrx) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

23.6.23 Data Register x (x = 0 to 15) (DTRx)

Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x).
This register is used only at transmission and reception of a data frame but not at transmission and reception
of a remote frame.
n Data register x (x = 0 to 15) (DTRx)
BYTE0
Address: 003A80 +8x (CAN0)
H
Address: 003B80 +8x (CAN1)
H
Read/write →
Initial value →
BYTE1
Address: 003A81 +8x (CAN0)
H
Address: 003B81 +8x (CAN1)
H
Read/write →
Initial value →
BYTE2
Address: 003A82 +8x (CAN0)
H
Address: 003B82 +8x (CAN1)
H
Read/write →
Initial value →
BYTE3
Address: 003A83 +8x (CAN0)
H
Address: 003B83 +8x (CAN1)
H
Read/write →
Initial value →
BYTE4
Address: 003A84 +8x (CAN0)
H
Address: 003B84 +8x (CAN1)
H
Read/write →
Initial value →
BYTE5
Address: 003A85 +8x (CAN0)
H
Address: 003B85 +8x (CAN1)
H
Read/write →
Initial value →
BYTE6
Address: 003A86 +8x (CAN0)
H
Address: 003B86 +8x (CAN1)
H
Read/write →
Initial value →
BYTE7
Address: 003A87 +8x (CAN0)
H
Address: 003B87 +8x (CAN1)
H
Read/write →
Initial value →
• Sets transmit message data (any of 0 to 8 bytes).
Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7 from the MSB.
• Stores receive message data.
Data is stored in the order of BYTE0, BYTE1, ..., BYTE7 from the MSB.
Even if the receive message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to
which data are stored, are undefined.
Note: A write operation to this register should be performed in word unit. A write operation in byte unit
causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the up-
per byte is ignored.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
7 6 5
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
15 14 13
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
15 14 13
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
15 14 13
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
15 14 13
D7 D6 D5
(R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
23-30
4 3 2
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
12 11 10
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
4 3 2
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
12 11 10
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
4 3 2
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
12 11 10
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
4 3 2
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
12 11 10
D4 D3 D2 D1
(R/W) (R/W) (R/W)
(X) (X) (X) (X)
← Bit No.
1 0
D0
(R/W)
(X)
← Bit No.
9 8
D0
(R/W)
(X)
← Bit No.
1 0
D0
(R/W)
(X)
← Bit No.
9 8
D0
(R/W)
(X)
← Bit No.
1 0
D0
(R/W)
(X)
← Bit No.
9 8
D0
(R/W)
(X)
← Bit No.
1 0
D0
(R/W)
(X)
← Bit No.
9 8
D0
(R/W)
(X)