Operation In Asynchronous Mode (Operation Mode 0 Or 1); Fig. 12.14 Format Of Transfer Data (Operation Mode 0 Or 1) - Fujitsu MB90420/5 (A) Series Hardware Manual

12.7.1 Operation in Asynchronous Mode (Operation Mode 0 or 1)

When the UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the
asynchronous transfer mode is selected.
n Operation in asynchronous mode
• Format of transfer data
Data transfer always starts with the start bit (L level) the specified data bits length is transfered on an LSB-
first and the data transfer ends with the stop bit (H level).
– In operation mode 0, without parity, the data is always 7-bit length; with parity, the data is always 8-bit
length.
– In operation mode 1, without parity, the data is always 8-bit length, but an A/D (address/data select bit)
is attached instead.
Figure 12.14 shows the data format for the asynchronous mode.
[Operation mode 0]
[Operation mode 1]
* : D7 (bit 7)....No parity
P (parity) ....With parity
ST : Start bit
SP : Stop bit
A/D : Address/data select bit for operation mode 1 (multiprocessor mode)
• Transmission
When the transmit data empty flag bit (SSR0/1: TDRE) is 1, transmit data is written to the output data
register (SODR). When the transmission is already enabled (SCR0/1: TXE = 1) at this point, data is
transmitted.
When the transmit data is transferred to the transmit shift register and transmission is started, the TDRE
flag is reset to 1 and the next transmit data is able to be set. When the transmit interrupt request is already
enabled (SSR0/1: TIE = 1) at this point, the transmit interrupt request is output to request the transmit data
to be set in SODR0/1. When the transmit data is written to SODR0/1, the TDRE flag is cleared to 0.
• Reception
When the reception is enabled (SCR0/1: RXE = 1), reception is being performed. When the start bit is
detected, one frame data is received according to the data format specified by the control register
(SCR0/1). When an error occurs after receiving the one frame data, the error flag is set and then the
receive data full flag bit (SSR0/1: RDRF) is set to 1. When the receive interrupt request is already
enabled (SSR0/1: RIE = 1) at this point, the receive interrupt request is output. Check each flag of the
status register (SSR0/1) and when reception is performed normally, read the input data register (SIDR0/1);
when an error occurs, handle the error. The RDRF flag is cleared to 0 when the receive data is read from
SIDR0/1.
• Stop bit
During transmission, one bit or two bits can be selected. However, the receive side always recognizes
only the first bit.
ST D0 D1
ST D0 D1

Fig. 12.14 Format of Transfer Data (operation mode 0 or 1)

UART
D2 D3 D4 D5 D6 D7/P SP
D2 D3 D4 D5 D6
12-29
*
D7 A/D SP