Fig. 4.1 Clock Supply Map - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F
• Clock supply map
Machine clocks generated by the clock generation section are supplied as operating clocks to the CPU and
resources. Consequently, the operation of the CPU and resources is affected by switching between the
main clock and the PLL clock (clock mode) or by switching the PLL clock multiplier. The clock-divided output
of the time-base timer is supplied to some resources, and the operating clock can be selected for each
resource. Figure 4.1 gives the clock supply map.
Clock generation section
X0A
Pin
Clock
generation
X1A
circuit
Pin
X0
Pin
Clock
generation
X1
circuit
HCLK
Pin
(Oscillation clock)
HCLK : Oscillation clock
MCLK : Main clock
PCLK : PLL clock
SCLK : Sub-clock
φ
: Machine clock
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
Time-base timer
1 2
PLL Multiplying circuit
SCLK
(Sub-clock)
4-devided clock
2-devided clock Clock selector
MCLK
(Machine clock)
(Main clock)

Fig. 4.1 Clock Supply Map

Low-voltage detection circuit/CPU
4
3 4
PCLK
(PLL clock)
φ
CPU
16-bit input capture 0/1/2/3
Stepping motor controller
4
Oscillation stabilization wait
4-4
Resources
operation detection circuit/
Watchdog timer
16-bit PPG timer 0/1/2
PPG0 to PPG2
CAN controller 0 (/1)
Sound generator
LCD controller/driver
COM0 to COM3
SEG0 to SEG23
UART0/1
SCK0, SCK1
SIN0, SIN1
Prescaler 0, 1
SOT0, SOT1
16-bit reload timer 0/1
Timepiece timer
TOT0, TOT1
External interrupt
INT0 to INT7
16-bit free-run timer
AN0 to AN7
10-bit A/D converter
PWM1P0 to PWM1P3
0/1/2/3
PWM1M0 to PWM1M3
PWM2P0 to PWM2P3
controller
PWM2M0 to PWM2M3
TRG
Pin
Pin
RX0 (,1)
Pin
TX0 (,1)
Pin
SGA, SG0
Pin
V0 to V3
Pin
Pin
Pin
Pin
Pin
TIN0, TIN1
Pin
Pin
WOT
Pin
Pin
IN0 to IN3
Pin
Pin
ADTG
Pin
Pin
Pin
Pin
Pin