Fujitsu MB90420/5 (A) Series Hardware Manual page 333

F2mc-16lx family 16-bit microcontrollers
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n PPG decrement counter register (PDCR)
This register can read the values of the 16-bit decrement counter.
Access this register using 16-bit data.
PPG decrement counter
register (upper)
Address: ch0 003921
Address: ch1 003929
Address: ch2 003931
PPG decrement counter
register (lower)
Address: ch0 003920
Address: ch1 003928
Address: ch2 003930
n PPG cycle setting register (PCSR)
This is the cycle setting register with a buffer. Transfer from the buffer is performed by causing a counter
borrow.
At initializing or changing the cycle setting register, always to write to the duty setting register after writing to
the cycle setting register.
Access the cycle setting register using 16-bit data.
PPG cycle setting register
(upper)
Address: ch0 003923
Address: ch1 00392B
Address: ch2 003933
PPG cycle setting register
(lower)
Address: ch0 003922
Address: ch1 00392A
Address: ch2 003932
n PPG duty setting register (PDUT)
This is the duty setting register with a buffer. Transfer from the buffer is performed by causing a counter
borrow.
When the value of the cycle setting register and the value of the duty setting register are the same, all Hs is
output when normal polarity is specified; all Ls is output when invert polarity is specified.
Do not set a value of "PCSR < PDUT". Otherwise, the PPG output becomes undefined.
Access the duty setting register using 16-bit data.
PPG duty setting register
(upper)
Address: ch0 003925
Address: ch1 00392D
Address: ch2 003935
PPG duty setting register
(lower)
Address: ch0 003924
Address: ch1 00392C
Address: ch2 003934
PPG TIMER
bit 15
bit 14
bit 13
DC15
DC14
DC13
H
H
(R)
(R)
(R)
H
(1)
(1)
(1)
bit 7
bit 6
DC07
DC06
H
H
(R)
(R)
H
(1)
(1)
bit 15
bit 14
bit 13
CS15
CS14
CS13
H
(W)
(W)
(W)
H
(X)
(X)
(X)
H
bit 7
bit 6
CS07
CS06
H
(W)
(W)
H
(X)
(X)
H
bit 15
bit 14
bit 13
DU15
DU14
DU13
H
H
(W)
(W)
(W)
(X)
(X)
(X)
H
bit 7
bit 6
DU07
DU06
H
H
(W)
(W)
H
(X)
(X)
bit 12
bit 11
bit 10
DC12
DC11
DC10
(R)
(R)
(R)
(1)
(1)
(1)
bit 5
bit 4
bit 3
DC05
DC04
DC03
(R)
(R)
(R)
(1)
(1)
(1)
bit 12
bit 11
bit 10
CS12
CS11
CS10
(W)
(W)
(W)
(X)
(x)
(X)
bit 5
bit 4
bit 3
CS05
CS04
CS03
(W)
(W)
(W)
(X)
(X)
(x)
bit 12
bit 11
bit 10
DU12
DU11
DU10
(W)
(W)
(W)
(X)
(x)
(X)
bit 5
bit 4
bit 3
DU05
DU04
DU03
(W)
(W)
(W)
(X)
(X)
(x)
13-9
bit 9
bit 8
DC09
DC08
PDCRH0 to 2
(R)
(R)
(1)
(1)
bit 2
bit 1
bit 0
DC02
DC01
DC00
(R)
(R)
(R)
(1)
(1)
(1)
bit 9
bit 8
CS09
CS08
PCSRH0 to 2
(W)
(W)
(X)
(X)
bit 2
bit 1
bit 0
CS02
CS01
CS00
(W)
(W)
(W)
(X)
(X)
(X)
bit 9
bit 8
DU09
DU08
PDUTH0 to 2
(W)
(W)
(X)
(X)
bit 2
bit 1
bit 0
DU02
DU01
DU00
(W)
(W)
(W)
(X)
(X)
(X)
Read/write
Initial value
PDCRL0 to 2
Read/write
Initial value
Read/write
Initial value
PCSRL0 to 2
Read/write
Initial value
Read/write
Initial value
PDUTL0 to 2
Read/write
Initial value

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